Cross-Level Processor Verification

Cross-level Processor Verification

Concept

Cross-level processor verification compares a processor implementation at the RTL level with a reference instruction set simulator in co-simulation. In the cited DATE 2022 approach, endless randomized instruction streams are guided by functional coverage and coverage-guided aging to exercise broad and deep processor behavior while detecting mismatches between the RTL core and ISS.

First seen 5/28/2026

Last seen 6/5/2026

Evidence 7 chunks

Wiki v2

WIKI

Overview

Cross-level processor verification is a processor-verification approach that compares behavior across abstraction levels, notably an RTL processor core and a reference instruction set simulator (ISS), in a co-simulation setup. In the cited DATE 2022 work, the ISS and RTL core are integrated into an efficient co-simulation compiled into a single binary with in-memory communication, and a comparator checks for functional differences between the two executions. [C1]

DATE 2022 coverage-guided approach

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← introduces 100% 7e

The paper proposes a novel cross-level verification approach for processor verification at the RTL.

Coverage-guided Aging uses → 100% 5e

The cross-level processor verification approach uses coverage-guided aging.

Cross-level processor verification targets RTL verification.

Co-simulation uses → 95% 4e

Cross-level processor verification uses co-simulation with an ISS as reference model.

Coverage-Observer ← part of 90% 2e

The Coverage-Observer is a component of the cross-level processor verification framework.

Instruction-Injector ← part of 90% 2e

The Instruction-Injector is a component of the cross-level processor verification framework.

Instruction Set Simulator (ISS) uses → 100% 2e

Cross-level verification uses an ISS as reference model.

Core Adapter ← part of 90% 1e

The Core-Adapter is a component of the cross-level processor verification framework.

Comparator ← part of 100% 1e

The Comparator is a component that finds functional differences between RTL-Core and ISS.

Randomized Instruction Stream Generation uses → 100% 1e

Cross-level processor verification is based on endless randomized instruction stream generation.

Co-Simulation uses → 100% 1e

Cross-level processor verification uses co-simulation with ISS

RTL uses → 100% 1e

Cross-level processor verification targets verification at the RTL level.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← introduces 95% 1e

The paper proposes a novel cross-level approach for processor verification at the RTL.

Instruction Set Architecture uses → 90% 1e

Cross-level verification compares processor behavior against an ISA specification.

Instruction Sequence State Space ← part of 80% 1e

The RISC-V instruction sequence state space is what the fuzzer explores during processor verification.

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging INTRODUCES Extracted graph relationship

Co-simulation USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] C1: Cross-level processor verification compares an RTL core with an ISS in efficient co-simulation and uses a comparator to detect functional differences. Cross-Level Processor Verification via

[2] C2: The DATE 2022 method uses a randomized coverage-guided instruction stream generator, runtime coverage information, an ISS reference model, and coverage-guided aging. Cross-Level Processor Verification via

[3] C3: The setup supports unrestricted instruction generation, including load/store instructions, CSR instructions, and infinite loops. Cross-Level Processor Verification via

[4] C4: The architecture uses components such as an instruction generator, instruction injector, core adapter, RTL core and memory, ISS and memory, coverage observer, and comparator; the core adapter handles RTL micro-architectural fetch effects. Cross-Level Processor Verification via

[5] C5: The coverage observer measures functional coverage from the ISS execution state, performs coverage aging, and guides the instruction injector with coverage hints. Cross-Level Processor Verification via

[6] C6: The comparator logs register-value changes and compares corresponding changes to handle timing differences between the RTL core and ISS, terminating simulation on differences. Cross-Level Processor Verification via

[7] C7: The evaluation used the MINRES The Good Core 32-bit pipelined RISC-V core, a SystemC-based RISC-V VP ISS, Verilator translation to C++, a SystemC test bench, and the RV32IMCZicsrZifencei subset. Cross-Level Processor Verification via