Randomized Instruction Stream Generation

Concept

Randomized Instruction Stream Generation is a processor-verification stimulus technique in which a random test generator produces instruction streams. In the cited cross-level verification work, a static randomized generator was effective for bug hunting but tended to favor particular test-state spaces during endless instruction-stream execution, producing coverage peaks and gaps that Coverage-guided Aging was designed to reduce.

First seen 5/29/2026

Last seen 6/8/2026

Evidence 11 chunks

Wiki v1

WIKI

Overview

Randomized Instruction Stream Generation refers to generating processor test stimuli as randomized instruction sequences or streams. In the cited cross-level processor-verification work, the random generator is described as a re-implementation of an existing test generator and as having already demonstrated strong bug-hunting capability. The same work uses the generator in an endless instruction-stream setting rather than as a sequence of isolated test cases.

Role in processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 6e

The paper's foundation is a randomized coverage-guided instruction stream generator.

Coverage-guided Aging ← uses 90% 2e

Coverage-guided Aging extends randomized instruction stream generation.

Constraint-based Test Generation ← compares with 85% 1e

The paper compares constraint-based test generation with randomized instruction stream generation.

Cross-Level Processor Verification ← uses 100% 1e

Cross-level processor verification is based on endless randomized instruction stream generation.

RISC-V ISA uses → 90% 1e

The randomized instruction stream generator produces RISC-V instructions.

Cryptographic Seed Initialization ← implements 90% 1e

Cryptographic seed initialization ensures deterministic random sources that provide the same random sequences.

riscv-dv ← uses 90% 1e

RISC-V DV uses randomized instruction stream generation as part of its test approach.

rand_instr_test ← uses 90% 1e

The rand_instr_test uses randomized instruction stream generation.

Instruction Stream Generator ← uses 90% 1e

The instruction stream generator produces endless randomized instruction streams.

LINKED ENTITIES

3 links

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

Coverage-guided Aging USES Extracted graph relationship

Instruction Stream Generator USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] The random generator is a re-implementation of an existing test generator and had already proven strong bug-hunting capability. Cross-Level Processor Verification via

[2] The baseline random generator uses a static randomized test strategy that does not change over time, which is problematic for endless instruction streams. Cross-Level Processor Verification via

[3] The random test generator produced substantial peaks for some instruction-group combinations and almost never executed other combinations, creating visible coverage gaps. Cross-Level Processor Verification via

[4] Coverage-guided Aging produced weaker peaks, executed every group in the reported comparison, and yielded a more balanced result with no visible gaps. Cross-Level Processor Verification via

[5] The cross-level verification setup executes generated instructions on an RTL core and ISS, measures functional coverage from ISS execution state, and uses the coverage observer to guide test generation over time. Cross-Level Processor Verification via