Instruction Stream Generator

CodeArtifact

The Instruction Stream Generator is a code artifact used in a RISC-V RTL co-simulation verification setup to produce an endless, unrestricted instruction stream. Its baseline strategy fully randomizes instructions, while guided modifications such as opcode injection increase the presence of legal instructions and steer testing toward interesting cases.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

The Instruction Stream Generator is part of a RISC-V cross-level co-simulation verification approach in which a generated instruction stream is supplied to both an RTL core under test and an Instruction Set Simulator (ISS) reference model. The broader testbench compares results after each executed instruction so that RTL errors can be detected immediately when they occur. [C1]

Generation model

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LINKED ENTITIES

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Co-Simulation Testbench CONTAINS Extracted graph relationship

On-the-Fly Instruction Stream Evolution IMPLEMENTS Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] C1: The generator is used in a RISC-V co-simulation setup where a testbench feeds the generated instruction stream to an ISS reference model and RTL core and compares results after each executed instruction. 2020FDL_cross-level-processor-verification-riscv.pdf

[2] C2: The Instruction Stream Generator supports endless unrestricted instruction generation, with a baseline algorithm that fully randomizes generated instructions. 2020FDL_cross-level-processor-verification-riscv.pdf

[3] C3: A generation modification injects a random instruction opcode to create a valid instruction while keeping instruction fields randomized, helping cover a large set of legal instructions. 2020FDL_cross-level-processor-verification-riscv.pdf

[4] C4: The approach supports memory access instructions, jump instructions including self-loops from on-the-fly generation, and special RISC-V CSR access instructions. 2020FDL_cross-level-processor-verification-riscv.pdf

[5] C5: Instruction matching uses a pending-instruction queue containing PC and instruction values fetched by the RTL core but not yet consumed by the ISS, and reports a mismatch if no match is found. 2020FDL_cross-level-processor-verification-riscv.pdf

[6] C6: The approach evolves the instruction stream on-the-fly during simulation to generate an endless instruction stream without restrictions. 2020FDL_cross-level-processor-verification-riscv.pdf