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Instruction Stream Generator

CodeArtifact WIKI v1 · 5/25/2026

The Instruction Stream Generator is a code artifact used in a RISC-V RTL co-simulation verification setup to produce an endless, unrestricted instruction stream. Its baseline strategy fully randomizes instructions, while guided modifications such as opcode injection increase the presence of legal instructions and steer testing toward interesting cases.

Overview

The Instruction Stream Generator is part of a RISC-V cross-level co-simulation verification approach in which a generated instruction stream is supplied to both an RTL core under test and an Instruction Set Simulator (ISS) reference model. The broader testbench compares results after each executed instruction so that RTL errors can be detected immediately when they occur. [C1]

Generation model

The generator is designed for endless generation of unrestricted instructions. In the baseline algorithm, generated instructions are fully randomized; this baseline forms the foundation of the testing process. The implementation also applies modifications that guide generation toward interesting cases. [C2]

One described modification injects a random instruction opcode to create a valid instruction while leaving the remaining instruction fields randomized. This is characterized as simple, generic, and effective, and it helps ensure that a large set of legal instructions is considered. [C3]

Supported instruction behavior

The co-simulation setup is described as supporting generated instruction streams without restrictions. The evidence explicitly states support for memory access instructions, jump instructions including self-loops caused by on-the-fly generation, and special RISC-V CSR access instructions. This breadth enables comprehensive testing while requiring the ISS and RTL core to behave identically on observable architectural state such as register updates. [C4]

Interaction with instruction matching

Unrestricted on-the-fly generation creates a synchronization challenge because a pipelined RTL core may prefetch instructions that are not ultimately executed after jumps or traps. Therefore, the instruction stream logic keeps a queue of pending instructions fetched by the RTL core but not yet consumed by the ISS, storing both the program counter and generated instruction. When the ISS requests the next instruction, the implementation searches this queue for a match on PC and expected instruction, returning the instruction on success or reporting a mismatch otherwise. [C5]

Role in the co-simulation testbench

The Instruction Stream Generator contributes the stimulus stream used by the co-simulation testbench. The testbench feeds the generated stream to both the ISS and the RTL core, while the surrounding infrastructure, including a core adapter, handles completion detection and architectural-state comparison. [C1] [C5]

Relationship to on-the-fly evolution

The generator implements the approach of evolving the instruction stream on-the-fly during simulation: instructions are generated dynamically as the RTL core and ISS fetch them, rather than from a fixed precomputed program. [C6]

LINKED ENTITIES

2 links
Co-Simulation Testbench CONTAINS
On-the-Fly Instruction Stream Evolution IMPLEMENTS

CITATIONS

6 sources
6 citations
[1] C1: The generator is used in a RISC-V co-simulation setup where a testbench feeds the generated instruction stream to an ISS reference model and RTL core and compares results after each executed instruction. 2020FDL_cross-level-processor-verification-riscv.pdf
[2] C2: The Instruction Stream Generator supports endless unrestricted instruction generation, with a baseline algorithm that fully randomizes generated instructions. 2020FDL_cross-level-processor-verification-riscv.pdf
[3] C3: A generation modification injects a random instruction opcode to create a valid instruction while keeping instruction fields randomized, helping cover a large set of legal instructions. 2020FDL_cross-level-processor-verification-riscv.pdf
[4] C4: The approach supports memory access instructions, jump instructions including self-loops from on-the-fly generation, and special RISC-V CSR access instructions. 2020FDL_cross-level-processor-verification-riscv.pdf
[5] C5: Instruction matching uses a pending-instruction queue containing PC and instruction values fetched by the RTL core but not yet consumed by the ISS, and reports a mismatch if no match is found. 2020FDL_cross-level-processor-verification-riscv.pdf
[6] C6: The approach evolves the instruction stream on-the-fly during simulation to generate an endless instruction stream without restrictions. 2020FDL_cross-level-processor-verification-riscv.pdf