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On-the-Fly Instruction Stream Evolution

Technique

On-the-Fly Instruction Stream Evolution is a processor-verification technique in which an endless, unrestricted instruction stream is evolved during simulation rather than generated as separate compile-and-run test cases. In the cited RISC-V RTL verification setup, the evolved stream is fed to both an RTL core and an Instruction Set Simulator reference model in a tightly coupled co-simulation environment, enabling instruction-by-instruction comparison and high-throughput testing.

First seen 5/25/2026
Last seen 5/25/2026
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WIKI

Overview

On-the-Fly Instruction Stream Evolution is a simulation-based processor verification technique that generates one endless instruction stream without restrictions on the generated instructions by evolving that stream during simulation. In the cited RISC-V RTL verification approach, the generated stream is fed to both the RTL core under test and an Instruction Set Simulator (ISS) used as a reference model, and results are compared after each executed instruction to detect RTL errors immediately when they occur. [C1]

Motivation

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CITATIONS

8 sources
8 citations — click to expand
[1] C1: The technique evolves an endless unrestricted instruction stream during simulation, feeds it to both an RTL core and ISS, and compares results after each executed instruction. 2020 FDL cross-level processor verification RISC-V PDF
[2] C2: Decoupled generate/compile/load/execute/compare flows make verification less efficient and make execution feedback to the test generation engine more difficult; the cited approach contrasts this with on-the-fly evolution. 2020 FDL cross-level processor verification RISC-V PDF
[3] C3: The evidence depicts the instruction generator producing next instructions for both RTL and ISS sides while RTL and ISS test memories behave in the same way. 2020 FDL cross-level processor verification RISC-V PDF
[4] C4: The instruction stream generator enables endless unrestricted instruction generation; its baseline fully randomizes instructions, and a modification injects random opcodes to create valid instructions while keeping fields randomized. 2020 FDL cross-level processor verification RISC-V PDF
[5] C5: The provided `InstrGenerator::next()` pseudocode continues an existing sequence when available and can start a new sequence with a random probability. 2020 FDL cross-level processor verification RISC-V PDF
[6] C6: Pipeline prefetch, jumps, and traps can cause RTL and ISS fetch streams to diverge; instruction stream matching uses pending instructions and reports mismatches when the ISS fetches an instruction not delivered to the RTL core. 2020 FDL cross-level processor verification RISC-V PDF
[7] C7: A core adapter observes internal RTL core signal changes, notifies the test controller on instruction completion, preserves order for illegal instructions, and provides RTL register values for ISS comparison. 2020 FDL cross-level processor verification RISC-V PDF
[8] C8: The approach is reported to process more than 200 million instructions per hour on a standard laptop and to have found several serious bugs in a 32-bit pipelined RISC-V core case study. 2020 FDL cross-level processor verification RISC-V PDF