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Randomized Instruction Stream Generation

Concept WIKI v1 · 5/30/2026

Randomized Instruction Stream Generation is a processor-verification stimulus technique in which a random test generator produces instruction streams. In the cited cross-level verification work, a static randomized generator was effective for bug hunting but tended to favor particular test-state spaces during endless instruction-stream execution, producing coverage peaks and gaps that Coverage-guided Aging was designed to reduce.

Overview

Randomized Instruction Stream Generation refers to generating processor test stimuli as randomized instruction sequences or streams. In the cited cross-level processor-verification work, the random generator is described as a re-implementation of an existing test generator and as having already demonstrated strong bug-hunting capability. The same work uses the generator in an endless instruction-stream setting rather than as a sequence of isolated test cases.

Role in processor verification

In the DATE 2022 cross-level verification setup, generated instructions are executed by both an RTL core and an instruction-set simulator (ISS), with results compared to find functional differences. The framework includes an instruction-generation component, a coverage observer, an instruction injector, and a comparator. The coverage observer measures functional coverage from the ISS execution state and can provide hints to guide later test generation.

Static random strategy and coverage behavior

The cited work characterizes the baseline random generator as using a static randomized test strategy that does not change over time. This is a limitation for endless instruction streams because the generator cannot be readjusted between separate runs as it could be for individual test cases.

In the reported comparison, instructions produced by the random test generator created substantial peaks for some combinations of instruction groups while other combinations were almost never executed. The paper gives examples where the Special & System : Special & System combination had a very low count, whereas Other : Other was executed very often. The authors therefore describe visible coverage gaps and say the random test generator result appears to degenerate over time.

Relationship to Coverage-guided Aging

The same work compares the static random generator with a generator enhanced by Coverage-guided Aging. The Coverage-guided Aging version had weaker peaks, executed every instruction-group combination in the reported coverage view, and produced clearly visible execution counts for every group. In that comparison, Coverage-guided Aging provided a more balanced result and no visible gaps, complementing the baseline randomized generator for long-running instruction streams.

LINKED ENTITIES

3 links
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES
Coverage-guided Aging USES
Instruction Stream Generator USES

CITATIONS

5 sources
5 citations
[1] The random generator is a re-implementation of an existing test generator and had already proven strong bug-hunting capability. Cross-Level Processor Verification via
[2] The baseline random generator uses a static randomized test strategy that does not change over time, which is problematic for endless instruction streams. Cross-Level Processor Verification via
[3] The random test generator produced substantial peaks for some instruction-group combinations and almost never executed other combinations, creating visible coverage gaps. Cross-Level Processor Verification via
[4] Coverage-guided Aging produced weaker peaks, executed every group in the reported comparison, and yielded a more balanced result with no visible gaps. Cross-Level Processor Verification via
[5] The cross-level verification setup executes generated instructions on an RTL core and ISS, measures functional coverage from ISS execution state, and uses the coverage observer to guide test generation over time. Cross-Level Processor Verification via