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Constraint-Based Test Generation

Concept

Constraint-based test generation is a test-program-generation paradigm in which instruction streams, initial states, and expected results are produced by solving or sampling a set of architectural and verification-target constraints. The supplied evidence traces this paradigm from early constraint-satisfaction formulations for processor test programs (Lewin et al., 1995) through its embodiment in the Genesys test-program generator (Aharon et al., DATE 1999) and its continued use in constraint-based specifications and abstract-CSP formulations of instruction-stream generation cited in DATE 2022 cross-level processor-verification work.

First seen 5/29/2026
Last seen 6/19/2026
Evidence 6 chunks
Wiki v2

WIKI

Overview

Constraint-based test generation is a test-program-generation approach in which the test inputs (instruction streams, initial processor states, and expected results) are produced by solving or sampling a set of constraints that encode architectural legality and verification-target rules. The supplied evidence traces this paradigm from early constraint-satisfaction formulations for processor test programs, through its embodiment in the Genesys test-program generator, and into more recent constraint-based specifications and abstract-CSP formulations of instruction-stream generation.

Foundational work

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NEIGHBORHOOD

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RELATIONSHIPS

8 connections
MicroTESK ← implements 90% 4e
MicroTESK is a specification-based tool for constructing test program generators using constraint-based techniques.
RISC-V Design Verification (DV) Framework ← uses 100% 4e
RISC-V DV applies constraint-based specification techniques to generate tests.
Genesys-Pro ← implements 90% 3e
Genesys-Pro implements innovations in test program generation for functional processor verification.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging compares with → 90% 2e
The paper discusses constraint-based test generation as a related approach.
Genesys mentions → 75% 1e
A referenced paper on constraint-based test generation is associated with Genesys development.
Google RISC-V Design Verification (DV) Framework ← uses 95% 1e
Google DV framework applies constraint-based specification techniques to generate tests.
Google RISC-V Design Verification (DV) Framework ← uses 95% 1e
Google's RISC-V DV framework uses constraint-based specifications to generate tests.
Randomized Instruction Stream Generation compares with → 85% 1e
The paper compares constraint-based test generation with randomized instruction stream generation.

LINKED ENTITIES

3 links
Genesys MENTIONS Extracted graph relationship
Genesys-Pro REFERENCES Genesys-Pro is explicitly cited in the DATE 2022 bibliography as 'innovations in test program generation for functional processor verification' and is a direct successor to Genesys in the constraint-based test-generation lineage.
MicroTESK REFERENCES MicroTESK is cited in the DATE 2022 bibliography as a 'specification-based tool for constructing test program generators' and represents a specification-based constraint-driven test-generation approach.

CITATIONS

5 sources
5 citations — click to expand
[1] The foundational constraint-satisfaction formulation for processor test-program generation was published by D. Lewin, L. Fournier, M. Levinger, E. Roytman, and G. Shurek at the IEEE 14th Phoenix Conference on Computers and Communications in 1995. Functional Verification Methodology for Microprocessors Using the Genesys Test Program Generator (DATE 1999)
[2] Genesys produces test files consisting of a sequence of instructions from a given initial state plus a section of expected results describing expected processor-resource values, and it solves the test-legality problem through directives files of varying degrees of control. Functional Verification Methodology for Microprocessors Using the Genesys Test Program Generator (DATE 1999)
[3] Genesys features a Testing Knowledge (TK) framework that allows incremental, external addition of constraints/biasing to the generator, e.g., to assign reasonable probability to corner cases such as a zero result from ADD or overlap of the two memory operands of a string instruction, and supports generation of fully random tests, specific scenarios, and test templates with varying levels of randomness. Functional Verification Methodology for Microprocessors Using the Genesys Test Program Generator (DATE 1999)
[4] The DATE 2022 cross-level processor-verification paper cites Genesys-Pro (Adir et al., 2004), 'Generating instruction streams using abstract CSP' (Katz, Rimon, and Ziv, 2012), and MicroTESK (Chupilko et al., 2017) as relevant test-program-generation work for functional processor verification. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (DATE 2022)
[5] The DATE 2022 paper describes a static randomized instruction generator that 'tends to favor specific test state spaces' because it is based on 'a static randomized test strategy that does not change over time,' producing substantial peaks in combinations such as Other : Other and leaving combinations such as Special & System : Special & System almost unexecuted, in contrast to the more balanced coverage-guided aging generator. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (DATE 2022)