Genesys

Tool

Genesys is an automatic pseudo-random test-program generator used in microprocessor design verification. The documented methodology uses a verification plan to induce targeted sets of tests, and Genesys was reported in a 1999 IBM Research/IEEE DATE paper as applied to verification of an x86 design.

First seen 5/24/2026

Last seen 6/9/2026

Evidence 11 chunks

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WIKI

Genesys

Overview

Genesys is a tool for microprocessor design verification. In the cited IBM Research/IEEE DATE 1999 work, it is described as an automatic pseudo-random test-program generator that promotes a functional verification methodology for microprocessors.

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NEIGHBORHOOD

6 nodes · 6 edges

graph · Genesys · depth=1

RELATIONSHIPS

13 connections

Code-based Test Generation for Validation of Functional Processor Descriptions ← mentions 100% 4e

The paper mentions Genesys as a typical tool for pseudo-random test generation.

Genesys PE compares with → 100% 2e

Genesys PE is compared to its predecessor Genesys in terms of verification productivity, quality and cost.

pseudo-random test generation uses → 100% 2e

Genesys is a tool for pseudo-random directed test generation.

Genesys PE ← extends 95% 2e

Genesys PE was developed as a successor and enhancement of Genesys with AI-based improvements.

IBM RISC System/6000 evaluates → 90% 1e

Genesys predecessor was used to verify the IBM RISC System/6000

microprocessor design verification uses → 1e

Genesys is used in the domain of microprocessor design verification.

Genesys-Pro ← extends 100% 1e

Genesys-Pro is the third-generation tool that extends and improves upon Genesys

Model-Based Test Program Generation implements → 100% 1e

Genesys is described as a model-based pseudorandom test program generator

pseudo-random test-program generation implements → 1e

Genesys implements pseudo-random test-program generation as an automatic test-program generator.

Verification Plan uses → 1e

Genesys uses a verification plan to induce smart sets of tests for verification tasks.

x86 evaluates → 1e

Genesys was applied to evaluate and verify an x86 design.

Random Test Program Generation implements → 95% 1e

Genesys implements random test program generation

x86 Architecture evaluates → 95% 1e

Genesys was used for functional verification of x86 microprocessors

LINKED ENTITIES

4 links

pseudo-random test-program generation IMPLEMENTS Extracted graph relationship

Verification Plan USES Extracted graph relationship

x86 EVALUATES Extracted graph relationship

microprocessor design verification USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Genesys is an automatic pseudo-random test-program generator for microprocessor functional verification. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family for DATE 1999 - IBM Research

[2] The Genesys-supported methodology relies on a verification plan that induces smart sets of tests for verification tasks. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family for DATE 1999 - IBM Research

[3] Genesys was reported as being used to verify an x86 design. Functional verification methodology for microprocessors using the Genesys test-program generator. Application to the x86 microprocessors family for DATE 1999 - IBM Research

[4] In pseudo-random hardware verification, small assembler sequences are generated by random but directed generators and used to compare HDL-model behavior with a functional simulator or ISS; Genesys is cited as a typical tool for this task. { Fabrice.Baray,Henri.Michel}

[5] The provided GitHub public context for allenai/genesys describes a Python repository for a distributed language-model architecture discovery system, which is not used as evidence for the microprocessor verification tool described in this article. allenai/genesys