Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator

Paper

First seen 6/19/2026

Last seen 6/19/2026

Evidence 5 chunks

NEIGHBORHOOD

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9 connections

x86 Architecture evaluates → 95% 2e

The paper reports on applying the methodology to verify an x86 microprocessor design.

The paper proposes and describes a functional verification methodology for microprocessors.

Genesys uses → 100% 2e

The paper uses Genesys as the primary test-program generator to demonstrate the methodology.

Genesys-x86 uses → 97% 2e

The paper reports a case study using Genesys-x86 for x86 microprocessor verification.

escape bugs evaluates → 93% 2e

The paper evaluates how the methodology could have prevented known escape bugs.

Yaron Arbetman authored by → 100% 1e

Yaron Arbetman is listed as an author of the paper.

Moshe Levinger authored by → 100% 1e

Moshe Levinger is listed as an author of the paper.

IBM Haifa Research Lab published by → 95% 1e

All authors are affiliated with IBM Haifa Research Lab.

Laurent Fournier authored by → 100% 1e

Laurent Fournier is listed as an author of the paper.