PowerPC

ISA

PowerPC is a processor instruction set architecture (ISA) studied as a target for formal compiler verification, as a target for just-in-time compilation, and as a subject of processor test-program generation and formal hardware-verification research.

First seen 5/24/2026

Last seen 6/27/2026

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PowerPC

PowerPC is a processor instruction set architecture (ISA) that has been studied as a target for formal compiler verification, as a target for just-in-time (JIT) compilation, and as a subject of processor test-program generation and formal hardware-verification research.

Role as a compiler target

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NEIGHBORHOOD

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RELATIONSHIPS

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PowerPC test program generator ← targets ISA 84% 1e

The generator is applied to verify processors implementing the PowerPC architecture, indicating it targets the PowerPC ISA.

PowerPC verification methodology ← targets ISA 82% 1e

The methodology is used to functionally verify IBM PowerPC processors, implying it targets the PowerPC architecture.

Formal model of PowerPC architecture ← derived from 88% 1e

The model represents the PowerPC architecture, indicating it is derived from and formalizes the ISA.

LINKED ENTITIES

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PowerPC test program generator TARGETS_ISA Extracted graph relationship

PowerPC verification methodology TARGETS_ISA Extracted graph relationship

Formal model of PowerPC architecture DERIVED_FROM Extracted graph relationship

CITATIONS

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[1] A formally verified compiler back-end has been developed from Cminor to PowerPC assembly code using the Coq proof assistant, proving semantic preservation for use in certification of critical software. A formally verified compiler back-end

[2] Microsoft's Shared Source CLI (Rotor) included a single-pass JIT compiler generating non-optimized code for Intel IA-32 and IBM PowerPC processors. An Optimizing Just-In-Time Compiler for Rotor

[3] A new methodology and test program generator were used at IBM for functional verification of six IBM PowerPC processors, containing a formal model of the PowerPC architecture and a heuristic database of testing expertise, used daily by about a hundred designers across four IBM sites for two years, reducing the functional verification period and time to market. Test program generation for functional verification of PowerPC processors in IBM

[4] The three PowerPC processors verified with this approach so far had fully functional first silicon despite the complexity of the PowerPC architecture. Test program generation for functional verification of PowerPC processors in IBM

[5] Testing processor conformance at the assembly level of an abstract model of the instruction set is particularly important because this level is the detail usually available for COTS processors and is the target level of high-level compilers. Test Program Generation for a Microprocessor: A Case Study

[6] The approach supports certification of COTS processors and bridges the gap between software certification (e.g., DO-178 in avionics) and hardware certification (e.g., DO-254 in avionics), addressing the needs of safety-critical systems such as fly-by-wire. Test Program Generation for a Microprocessor: A Case Study

[7] Prior formal hardware-verification work on PowerPC includes 'Formal verification of a PowerPC microprocessor' by Appenzeller and Kuehlmann at the 1995 IEEE International Conference on Computer Design (ICCD '95), pages 79-84. Test Program Generation for a Microprocessor: A Case Study