PowerPC verification methodology
TechniqueA methodology and automated test program generator developed and used by IBM for the functional verification of PowerPC processors, combining a formal architectural model with a heuristic testing-expertise database to shorten verification cycles and time-to-market.
First seen 6/27/2026
Last seen 6/27/2026
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PowerPC verification methodology
Overview
The PowerPC verification methodology is an IBM-developed approach to functional verification of PowerPC processors. It pairs a formal architectural model of the PowerPC instruction set with a heuristic database of testing expertise, and is delivered through an automated test program generator used daily by verification teams across multiple IBM sites.
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1 connectionsThe methodology is used to functionally verify IBM PowerPC processors, implying it targets the PowerPC architecture.
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1 linksCITATIONS
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[1] A new methodology and test program generator were used for the functional verification of six IBM PowerPC processors. Test program generation for functional verification of PowerPC processors in IBM
[2] The generator contains a formal model of the PowerPC architecture and a heuristic database of testing expertise. Test program generation for functional verification of PowerPC processors in IBM
[3] The methodology was used on a daily basis for two years by about one hundred designers and testing engineers across four IBM sites. Test program generation for functional verification of PowerPC processors in IBM
[4] The methodology significantly reduced the functional verification period and time to market of the PowerPC processors. Test program generation for functional verification of PowerPC processors in IBM
[5] The three processors verified so far had fully functional first silicon. Test program generation for functional verification of PowerPC processors in IBM