PowerPC

ISA

PowerPC is a RISC instruction set architecture created by the 1991 Apple–IBM–Motorola alliance. Since 2006 the evolving instruction set has been named Power ISA, while the PowerPC name remains associated with some Power Architecture implementations. The ISA has been used as a target in formal compiler verification, just-in-time compiler work, and processor conformance or verification research.

First seen 5/24/2026

Last seen 5/26/2026

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PowerPC

PowerPC is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, also known as AIM. Since 2006, the evolving instruction set has been named Power ISA, while the older PowerPC name continues as a trademark for some Power Architecture–based processor implementations.[1]

Role as a compiler target

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[1] PowerPC is a RISC ISA created by the 1991 Apple–IBM–Motorola alliance, and the evolving instruction set has been named Power ISA since 2006 while PowerPC remains a trademark for some Power Architecture implementations. PowerPC

[2] A formally verified compiler back-end from Cminor to PowerPC assembly used Coq for implementation and proof of semantic preservation, with relevance to certification of critical software. A formally verified compiler back-end

[3] Rotor included a single-pass JIT compiler that generated non-optimized code for Intel IA-32 and IBM PowerPC processors. An Optimizing Just-In-Time Compiler for Rotor

[4] Processor conformance testing can target an abstract model of the instruction set at the assembly level, which is important because that level is often available for COTS processors and is the target level of high-level compilers. Test Program Generation for a Microprocessor: A Case Study

[5] The cited verification literature includes a 1995 work titled 'Formal verification of a powerpc microprocessor.' Test Program Generation for a Microprocessor: A Case Study