Code-based Test Generation for Validation of Functional Processor Descriptions
PaperFirst seen 5/31/2026
Last seen 6/5/2026
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50 connectionsThe paper mentions SystemC as a functional modeling language for microprocessors.
The paper bases its work on the paradigm of Constraint Logic Programming.
The paper uses path coverage criterion as the test generation strategy.
The paper uses path enumeration to generate one constraint store per path.
The paper mentions IDL as the STMicroelectronics proprietary language from which x is derived.
The paper introduces the STCS dedicated constraint solver.
The paper uses the control flow vector to enumerate all paths.
The paper mentions Genesys as a typical tool for pseudo-random test generation.
The paper uses reified constraints to handle boolean expressions in assignments.
The paper evaluates the generated test suite using statement coverage.
The paper uses control flow graphs to analyze program paths.
The paper mentions mutation testing as potential future work.
Philippe Codognet is listed as a co-author of the paper.
Fabrice Baray is listed as a co-author of the paper.
The paper handles delayed assignments in the x language during constraint generation.
Henri Michel is listed as a co-author of the paper.
The paper introduces the STTVC tool for test vector construction.
Daniel Diaz is listed as a co-author of the paper.
The paper mentions Verilog as a hardware description language.
The paper mentions VHDL as a hardware description language.
The paper mentions Specman from Verisity Inc. as an alternative test generation tool.
The paper uses a symbolic solver to detect impractical paths
The paper mentions comparison of their constraint solver with SAT techniques as future work.
The paper mentions hardware verification as a key use case for simulation models
The paper defines and introduces the x language as its input language for functional processor descriptions.
The paper uses static analysis to translate the hardware description into constraint stores.
The paper uses constraint solving techniques to generate test vectors.
The paper uses SSA form concepts for array manipulation in constraint generation.
The paper frames test generation as a constraint satisfaction problem.
The paper mentions flexsim technology at STMicroelectronics.
The paper addresses code-based test generation as its core methodology.
The paper uses constraint solving techniques to generate test vectors.
The paper references SSA form for array manipulation techniques.
The paper uses Bell numbers to characterize the combinatorial complexity of index relationships.
The constraint solver uses arc consistency techniques for domain reduction.
The paper introduces and uses specific bit manipulation constraints in the solver.
The paper mentions pseudo-random test generation as a standard approach in hardware verification.
The paper mentions GNU Prolog as an existing solver that was considered but found insufficient.
Author Philippe Codognet is affiliated with University of Paris 6 LIP6
Author Daniel Diaz is affiliated with University of Paris 1
The paper uses domain reduction techniques in the constraint solver.
The paper introduces and uses the tabRead constraint for array reads.
The paper mentions VHDL as a hardware description language.
The paper mentions SystemC as a language for functional processor descriptions.
The paper mentions Bell numbers in the context of array index relationship enumeration.
The paper presents a code-based test generation approach for microprocessor functional models.
The paper generates constraint stores for each path to be used in test vector generation.
The paper introduces and mentions the alias coverage criterion for array index relationships.
The paper introduces and uses the tabWrite constraint for array writes.
The paper evaluates the approach on the STM7 micro-controller as a case study.