VHDL

Concept

VHDL is presented in the evidence as a hardware description language used for processor-core source code and supported by ITL-based verification workflows. In the cited ISS-generation work, VHDL record data types model architectural state, while ITL supports VHDL operators and data types such as arrays, user-defined types, and nested records.

First seen 5/26/2026

Last seen 6/9/2026

Evidence 7 chunks

Wiki v1

WIKI

Overview

VHDL is referenced as a hardware description language alongside Verilog in the context of ITL-based formal properties for synchronous sequential systems. In ITL temporal expressions, standard operators from the respective HDL language—VHDL or Verilog—can be used together with temporal operators such as next and prev.[C1]

Data types and modeling use

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NEIGHBORHOOD

2 nodes · 1 edges

graph · VHDL · depth=1

RELATIONSHIPS

3 connections

Code-based Test Generation for Validation of Functional Processor Descriptions ← mentions 100% 3e

The paper mentions VHDL as a hardware description language.

ITL ← uses 95% 2e

ITL supports the use of VHDL operators in temporal expressions.

RTL Design ← uses 100% 1e

RTL designs can be expressed using VHDL hardware description language.

LINKED ENTITIES

1 links

Instruction Set Simulator used_in_generation_workflow The evidence describes architectural state modeled with a VHDL record data type in a workflow whose reformulated properties are used to generate a C++ instruction set simulator.

CITATIONS

6 sources

6 citations — click to expand

[1] VHDL is referenced as an HDL whose standard operators can be used in ITL temporal expressions. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] ITL supports HDL data types including arrays, user-defined types, and nested record data types in VHDL. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] Architectural state can be established using a user-defined VHDL record data type that combines elements such as a register file, status flags, and a program counter. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] If verification is performed in architectural style, an ISS can be generated from the verification without manual steps in between. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] A reformulated architectural-style property can capture the verified design behavior and provide a formally checkable ISA description used to generate a C++ ISS. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] One reported processor core comprised about 10,000 lines of VHDL, while its reformulated property suite comprised 2,000 lines of ITL and was checked for completeness against the design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite