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STIMSMITH

SystemC

Concept

SystemC is a C++ class library with an event-driven simulation kernel, used with TLM as an industry-proven modeling standard for designs at multiple abstraction levels. In the cited processor-verification evidence, SystemC is used to implement a co-simulation testbench that connects an RTL core and an ISS reference model.

First seen 5/26/2026
Last seen 6/9/2026
Evidence 13 chunks
Wiki v1

WIKI

Overview

SystemC is described in the evidence as a C++ class library, not a separate new language, that includes an event-driven simulation kernel. In combination with TLM, it is characterized as an industry-proven modeling standard for building designs at different levels of abstraction. [SystemC nature]

Modeling structure

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NEIGHBORHOOD

3 nodes · 3 edges
graph · SystemC · depth=1

RELATIONSHIPS

11 connections
Code-based Test Generation for Validation of Functional Processor Descriptions ← mentions 100% 5e
The paper mentions SystemC as a functional modeling language for microprocessors.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e
The co-simulation testbench is implemented in SystemC.
co-simulation testbench ← uses 100% 2e
The co-simulation testbench is implemented using SystemC.
Virtual Prototype ← uses 90% 2e
Virtual prototypes use SystemC for hardware peripheral modeling
RISC-V VP ← uses 100% 2e
RISC-V VP uses SystemC for hardware modeling
Co-Simulation Testbench ← uses 100% 2e
The co-simulation testbench is implemented in SystemC.
x language ← implements 100% 1e
The x language is the functional subset of SystemC.
x language ← derived from 100% 1e
The x language is the functional subset of SystemC.
SimSoC ← uses 95% 1e
SimSoC uses the SystemC kernel to simulate hardware parallelism
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 1e
The paper uses SystemC for simulation
x language ← derived from 92% 1e
The x language is described as the functional subset of SystemC

LINKED ENTITIES

1 links
RTL models_communicate_via_signals The evidence states that communication can be implemented via signals, which are commonly used for RTL models.

CITATIONS

6 sources
6 citations — click to expand
[1] SystemC nature 2020FDL_cross-level-processor-verification-riscv.pdf
[2] SystemC execution model 2020FDL_cross-level-processor-verification-riscv.pdf
[3] SystemC communication 2020FDL_cross-level-processor-verification-riscv.pdf
[4] SystemC co-simulation testbench 2020FDL_cross-level-processor-verification-riscv.pdf
[5] Embedding generated C++ RTL 2020FDL_cross-level-processor-verification-riscv.pdf
[6] TLM memory abstraction 2020FDL_cross-level-processor-verification-riscv.pdf