Google RISC-V Design Verification (DV) Framework

Tool

Google RISC-V Design Verification (DV) Framework is an open-source processor verification tool for RISC-V RTL designs. It uses SystemVerilog constraint-based specifications to generate RISC-V assembly tests, runs a co-simulation flow with an Instruction Set Simulator (ISS) as a reference model, and compares ISS and RTL execution through log files.

First seen 5/30/2026

Last seen 5/30/2026

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Wiki v1

WIKI

Overview

Google RISC-V Design Verification (DV) Framework is described in the DATE 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging as an open-source RISC-V processor verification framework. The paper places it in the class of simulation-based RTL processor verification methods that use co-simulation with an Instruction Set Simulator (ISS) as a functional reference model for the RTL processor under test.

Test generation model

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← compares with 90% 2e

The paper compares its approach with Google's RISC-V DV framework, pointing out its weaknesses.

Constraint-based Test Generation uses → 95% 1e

Google DV framework applies constraint-based specification techniques to generate tests.

SystemVerilog uses → 95% 1e

Google DV framework uses SystemVerilog for its constraint-based specifications.

Co-simulation uses → 90% 1e

Google DV framework employs co-simulation with an ISS.

Instruction Set Simulator (ISS) uses → 90% 1e

Google DV framework uses an ISS as a functional reference model.

Google part of → 95% 1e

Google developed the open-source RISC-V DV framework.

Google ← uses 95% 1e

The RISC-V DV framework is Google's open-source tool.

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging COMPARES_WITH Extracted graph relationship

Constraint-based Test Generation USES Extracted graph relationship

SystemVerilog USES Extracted graph relationship

Co-simulation USES Extracted graph relationship

Instruction Set Simulator (ISS) USES Extracted graph relationship

Google PART_OF Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Google RISC-V DV is described as Google's open-source RISC-V Design Verification framework. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[2] The framework uses constraint-based specification techniques in SystemVerilog to generate RISC-V assembly tests one after another. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[3] Different RISC-V instruction sets are supported by selecting and combining the respective constraint-based specifications. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[4] The framework uses co-simulation with an ISS as the reference model and compares ISS and RTL execution results through execution log files. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[5] The cited paper reports limitations including restricted generated tests, short per-test sequences with resets, filesystem-based co-simulation overhead, and lack of dynamic coverage guidance from execution progress. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[6] The cited paper contrasts Google RISC-V DV with an approach using endless instruction streams, ISS/RTL integration into a single binary, in-memory communication, and dynamically updated coverage information. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging