Instruction Set Simulator (ISS)

Tool

In the provided cross-level processor verification flow, an Instruction Set Simulator (ISS) is used as the reference model in tight co-simulation with an RTL core. Coverage is measured from the ISS execution state, while a comparator checks ISS and RTL register-value changes to detect functional differences.

First seen 5/26/2026

Last seen 6/2/2026

Evidence 10 chunks

Wiki v2

WIKI

Overview

In the evidenced cross-level processor verification approach, the Instruction Set Simulator (ISS) is used as a reference model alongside an RTL core. The setup integrates the ISS and RTL core in an efficient co-simulation compiled into a single binary with in-memory communication. The approach generates endless instruction streams and uses the ISS reference execution as part of the verification loop. [C1]

Role in coverage-guided co-simulation

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RELATIONSHIPS

10 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 5e

The paper uses ISS as a reference model in co-simulation

Cross-Level Testing ← uses 100% 3e

Cross-level testing uses an ISS as a reference model.

Coverage-Observer ← uses 100% 2e

Coverage-Observer observes ISS execution state for coverage

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses an ISS as a reference model for RTL verification.

Comparator ← uses 100% 2e

Comparator compares ISS and RTL-Core register values

Co-Simulation Testbench ← uses 100% 2e

The co-simulation testbench uses the ISS as a reference model for comparison with the RTL core.

Core-Adapter ← uses 90% 2e

Core-Adapter checks for addresses not fetched by ISS and fills them

Comparator (RTL vs ISS) ← uses 90% 1e

The Comparator compares results between the ISS and the RTL core.

Google RISC-V Design Verification (DV) Framework ← uses 90% 1e

Google DV framework uses an ISS as a functional reference model.

RISC-V VP part of → 100% 1e

The RISC-V VP includes an ISS that is used as the reference model.

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

Google RISC-V Design Verification (DV) Framework USES Extracted graph relationship

Coverage-Observer USES Extracted graph relationship

Comparator USES Extracted graph relationship

Core-Adapter USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] The ISS is used as a reference model in a tight co-simulation with an RTL core, compiled into a single binary with in-memory communication. Cross-Level Processor Verification via

[2] Coverage information is continuously updated based on the execution state of the ISS and used with Coverage-guided Aging. Cross-Level Processor Verification via

[3] After execution, the RTL core and ISS write results to separated memories; the Coverage-Observer measures functional coverage from the ISS execution state, performs coverage aging, and gives hints to the Instruction-Injector. Cross-Level Processor Verification via

[4] The Comparator compares ISS and RTL register values, logs value changes to account for timing differences, and exits the simulation when it finds differences. Cross-Level Processor Verification via

[5] The Core Adapter handles RTL fetch effects by checking addresses not fetched by the ISS, filling them with randomized values not generated by InstrGen, and forwarding them to the RTL core. Cross-Level Processor Verification via

[6] The evaluation used a 32-bit pipelined RISC-V TGC core as DUT, the ISS from the open-source SystemC-based RISC-V VP as reference, Verilator for RTL-to-C++ translation, and a SystemC test bench; both core and ISS supported RV32IMCZicsrZifencei. Cross-Level Processor Verification via

[7] The reported experiments used a 1-second SystemC simulation time limit, approximately 20 million instructions. Cross-Level Processor Verification via