RISC-V VP
ToolRISC-V VP (riscv-vp) is a RISC-V virtual prototype and instruction-set-simulator reference used in cross-level processor-verification work. The provided evidence identifies its public repository at github.com/agra-uni-bremen/riscv-vp, documents comparisons against the RISC-V VP ISS in coverage-guided fuzzing, and notes RISCV-VP++ as an extended and improved successor.
First seen 5/26/2026
Last seen 9/5/2026
Evidence 78 chunks
Wiki v3
WIKI
Overview
RISC-V VP (riscv-vp) is a RISC-V virtual-prototype tool with a public repository identified in verification literature as https://github.com/agra-uni-bremen/riscv-vp. [RISC-V VP repository]
The provided evidence specifically documents the tool through its RISC-V VP ISS in processor-verification experiments. In a coverage-guided fuzzing study, VexRiscv behavior was compared against the RISC-V VP ISS, and the paper describes the VP decoder in that context as an RV32IM decoder that did not support the compressed-instruction extension RV32C. [RISC-V VP ISS and decoder]
NEIGHBORHOOD
5 nodes · 9 edgesgraph · RISC-V VP · depth=1
RELATIONSHIPS
50 connectionsRISC-V VP is the virtual prototype counterpart to MicroRV32 for cross-level verification.
FP-RVVTS evaluates RISC-V VP++ as a DUT.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 7e
The paper references RISC-V VP as used in the experimental setup.
RISC-V VP++ is SystemC-based.
The paper uses the ISS from RISC-V VP as the reference model for verification.
RISC-V VP implements the RISC-V instruction set architecture
RISC-V VP is an instance of a Virtual Prototype
The paper uses RISC-V VP's ISS as the reference model in the co-simulation.
CHERI-RISC-V VP++ is an extension of the existing RISC-V VP++ virtual prototype.
RISC-V VP includes an instruction set simulator as its simulation core.
RISC-V VP++ has a variant that uses SoftFloat.
RISC-V VP++ has a variant that uses FloppyFloat.
RISC-V VP++ is a RISC-V instruction set simulator used as a DUT.
The paper evaluates and verifies the RISC-V VP
RISC-V VP is a virtual prototype that includes an ISS used as reference model.
The paper uses the RISC-V VP's ISS as the reference model.
RISC-V VP uses TLM formalism to model hardware components.
RISC-V VP++ supports complex application processor-based systems with virtual memory.
The paper evaluates the RISC-V VP simulator for compliance testing.
RISC-V VP includes a TLM PLIC implementation as one of its components.
RISC-V VP implements the privileged architecture including CSRs
RISC-V VP provides the TLM PLIC reference model used in the methodology.
The paper evaluates RISC-V VP++ as a DUT using RVVTS.
RVVTS applies test sets on RISC-V VP++ as a DUT.
RISC-V VP supports booting Linux
RISC-V VP supports FreeRTOS
The paper evaluates RISC-V VP++ and finds bugs in its FP implementation.
RISC-V VP supports design space exploration
Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures ← evaluates 95% 2e
The paper evaluates the CHERI extension integrated into the RISC-V VP to assess IMC-based acceleration.
RISC-V VP is implemented using SystemC TLM
RISC-V VP++ uses Transaction Level Modeling for communication abstraction.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e
The paper evaluates the approach using RISC-V VP as one of the target simulators
The paper presents the RISC-V VP as its main contribution
The extended RISC-V VP models an IMC-based acceleration of CHERI tagged memory.
The RISC-V VP provides a HiFive1 board configuration
The RISC-V VP++ paper introduces the RISC-V VP++ virtual prototype.
The RISC-V VP is used as execution engine for concolic testing of embedded SW
The RISC-V VP is combined with CGF for verification of embedded RISC-V SW binaries
The RISC-V VP is combined with DIFT for information flow analysis
The paper uses RISC-V VP as the virtual prototype counterpart for cross-level verification.
The generated benchmarks are applied to the RISC-V VP for evaluation.
RISC-V VP supports Eclipse IDE for graphical debugging
RISC-V VP uses GDB RSP for software debugging
RISC-V VP++ was developed and is maintained by the Institute for Complex Systems, JKU Linz.
RISC-V VP++ includes the Load Store Cache as an ISS optimization component.
RISC-V VP++ includes the Dynamic Base Block Cache as an ISS optimization component.
RISC-V VP++ includes a TLB for virtual address translation.
RISC-V VP++ includes an MMU for virtual address translation.
RISC-V VP integrates a timing model for extra-functional property evaluation
RISC-V VP is written in SystemC TLM.
LINKED ENTITIES
3 linksCross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship
RISC-V IMPLEMENTS Extracted graph relationship
RISC-V VP SUCCEEDED_BY Public GitHub context describes RISCV-VP++ as an extended and improved successor of the RISC-V VP virtual prototype.
CITATIONS
5 sources5 citations — click to expand
[2] RISC-V VP ISS and decoder Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] CSR comparison findings Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] Compressed instruction mtval mismatch Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing