RISC-V VP

Tool

RISC-V VP (riscv-vp) is a RISC-V virtual prototype and instruction-set-simulator reference used in cross-level processor-verification work. The provided evidence identifies its public repository at github.com/agra-uni-bremen/riscv-vp, documents comparisons against the RISC-V VP ISS in coverage-guided fuzzing, and notes RISCV-VP++ as an extended and improved successor.

First seen 5/26/2026

Last seen 7/19/2026

Evidence 46 chunks

Wiki v3

WIKI

Overview

RISC-V VP (riscv-vp) is a RISC-V virtual-prototype tool with a public repository identified in verification literature as https://github.com/agra-uni-bremen/riscv-vp. [RISC-V VP repository]

The provided evidence specifically documents the tool through its RISC-V VP ISS in processor-verification experiments. In a coverage-guided fuzzing study, VexRiscv behavior was compared against the RISC-V VP ISS, and the paper describes the VP decoder in that context as an RV32IM decoder that did not support the compressed-instruction extension RV32C. [RISC-V VP ISS and decoder]

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NEIGHBORHOOD

13 nodes · 22 edges

graph · RISC-V VP · depth=1

RELATIONSHIPS

35 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 7e

The paper references RISC-V VP as used in the experimental setup.

SystemC uses → 100% 5e

RISC-V VP++ is SystemC-based.

FP-RVVTS ← evaluates 100% 5e

FP-RVVTS evaluates RISC-V VP++ as a DUT and identifies multiple bugs.

Virtual Prototype implements → 100% 4e

The RISC-V VP is an open-source virtual prototype for RISC-V systems.

Processor Verification using Symbolic Execution: A RISC-V Case-Study ← uses 100% 4e

The paper uses the ISS from RISC-V VP as the reference model for verification.

RISC-V implements → 100% 3e

RISC-V VP++ is a RISC-V virtual prototype.

SoftFloat uses → 100% 3e

RISC-V VP++ has a variant that uses SoftFloat.

Virtual Prototype (VP) implements → 100% 3e

RISC-V VP++ is a SystemC TLM-based Virtual Prototype.

FloppyFloat uses → 100% 3e

RISC-V VP++ has a variant that uses FloppyFloat.

CHERI-RISC-V VP++ ← extends 100% 3e

CHERI-RISC-V VP++ is an extension of the existing RISC-V VP++ virtual prototype.

RVVTS ← uses 100% 2e

RVVTS applies test sets on RISC-V VP++ as a DUT.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses the RISC-V VP's ISS as the reference model.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 2e

The paper uses RISC-V VP as the reference ISS in the co-simulation.

Instruction Set Simulator (ISS) implements → 95% 2e

RISC-V VP provides the ISS used as reference model in the paper.

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e

The paper evaluates the approach using RISC-V VP as one of the target simulators

Transaction Level Modeling uses → 95% 2e

RISC-V VP++ uses Transaction Level Modeling for communication abstraction.

virtual memory management implements → 90% 2e

RISC-V VP++ supports complex application processor-based systems with virtual memory.

Instruction Set Simulator (ISS) ← part of 100% 2e

RISC-V VP contains an ISS used as a reference model.

Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators ← evaluates 100% 2e

The paper evaluates RISC-V VP++ and finds bugs in its FP implementation.

Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures ← evaluates 95% 2e

The paper evaluates the CHERI extension integrated into the RISC-V VP to assess IMC-based acceleration.

In-Memory Computing uses → 90% 2e

The extended RISC-V VP models an IMC-based acceleration of CHERI tagged memory.

Single instruction isolation for RISC-V vector test failures ← evaluates 100% 2e

The paper evaluates RISC-V VP++ as a DUT using RVVTS.

Instruction Set Simulator (ISS) ← part of 100% 1e

The RISC-V VP includes an ISS that is used as the reference model.

Instruction Set Simulator implements → 95% 1e

RISC-V VP++ includes an Instruction Set Simulator as its core CPU model.

interpreter-based ISS implements → 100% 1e

RISC-V VP++ uses a fast interpreter-based ISS.

RISC-V Vector extension implements → 100% 1e

RISC-V VP++ supports the RISC-V Vector Extension.

CHERI Early Benchmarks uses → 95% 1e

The generated benchmarks are applied to the RISC-V VP for evaluation.

SystemC TLM uses → 100% 1e

RISC-V VP is written in SystemC TLM.

RISC-V VP++: Next generation open-source virtual prototype ← introduces 100% 1e

The RISC-V VP++ paper introduces the RISC-V VP++ virtual prototype.

CHERI implements → 95% 1e

The RISC-V VP is extended with the CHERI extension for RISC-V.

Translation Lookaside Buffer ← part of 90% 1e

RISC-V VP++ includes a TLB for virtual address translation.

memory management unit ← part of 90% 1e

RISC-V VP++ includes an MMU for virtual address translation.

Dynamic Base Block Cache ← part of 90% 1e

RISC-V VP++ includes the Dynamic Base Block Cache as an ISS optimization component.

Load Store Cache ← part of 90% 1e

RISC-V VP++ includes the Load Store Cache as an ISS optimization component.

Institute for Complex Systems, Johannes Kepler University Linz authored by → 95% 1e

RISC-V VP++ was developed and is maintained by the Institute for Complex Systems, JKU Linz.

LINKED ENTITIES

3 links

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RISC-V VP SUCCEEDED_BY Public GitHub context describes RISCV-VP++ as an extended and improved successor of the RISC-V VP virtual prototype.

CITATIONS

5 sources

5 citations — click to expand

[1] RISC-V VP repository Cross-Level Processor Verification via

[2] RISC-V VP ISS and decoder Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] CSR comparison findings Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] Compressed instruction mtval mismatch Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] RISCV-VP++ successor ics-jku/riscv-vp-plusplus