RISC-V VP — STIMSMITH

RISC-V VP

Tool

RISC-V VP (riscv-vp) is a RISC-V virtual prototype and instruction-set-simulator reference used in cross-level processor-verification work. The provided evidence identifies its public repository at github.com/agra-uni-bremen/riscv-vp, documents comparisons against the RISC-V VP ISS in coverage-guided fuzzing, and notes RISCV-VP++ as an extended and improved successor.

First seen 5/26/2026

Last seen 6/9/2026

Evidence 12 chunks

Wiki v3

WIKI

Overview

RISC-V VP (riscv-vp) is a RISC-V virtual-prototype tool with a public repository identified in verification literature as https://github.com/agra-uni-bremen/riscv-vp. [RISC-V VP repository]

The provided evidence specifically documents the tool through its RISC-V VP ISS in processor-verification experiments. In a coverage-guided fuzzing study, VexRiscv behavior was compared against the RISC-V VP ISS, and the paper describes the VP decoder in that context as an RV32IM decoder that did not support the compressed-instruction extension RV32C. [RISC-V VP ISS and decoder]

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NEIGHBORHOOD

5 nodes · 5 edges

graph · RISC-V VP · depth=1

RELATIONSHIPS

9 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 7e

The paper references RISC-V VP as used in the experimental setup.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses the RISC-V VP's ISS as the reference model.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 2e

The paper uses RISC-V VP as the reference ISS in the co-simulation.

RISC-V implements → 100% 2e

riscv-vp is a RISC-V virtual prototype/ISS.

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e

The paper evaluates the approach using RISC-V VP as one of the target simulators

SystemC uses → 100% 2e

RISC-V VP uses SystemC for hardware modeling

Virtual Prototype implements → 100% 1e

RISC-V VP provides a full virtual prototype

Instruction Set Simulator (ISS) ← part of 100% 1e

The RISC-V VP includes an ISS that is used as the reference model.

SystemC TLM uses → 100% 1e

RISC-V VP is written in SystemC TLM.

LINKED ENTITIES

3 links

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RISC-V VP SUCCEEDED_BY Public GitHub context describes RISCV-VP++ as an extended and improved successor of the RISC-V VP virtual prototype.

CITATIONS

5 sources

5 citations — click to expand

[1] RISC-V VP repository Cross-Level Processor Verification via

[2] RISC-V VP ISS and decoder Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] CSR comparison findings Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] Compressed instruction mtval mismatch Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] RISCV-VP++ successor ics-jku/riscv-vp-plusplus