SystemC TLM

Tool

SystemC TLM is used in the provided evidence as a modeling and co-simulation technology for virtual prototypes and processor-verification testbenches. The RISC-V VP reference model is described as a virtual prototype written in SystemC TLM, and a processor-verification study embeds a Verilated RTL core and the RISC-V VP ISS into a common SystemC testbench.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 1 chunks

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Overview

SystemC TLM appears in the provided evidence as the implementation technology for virtual-prototype and co-simulation workflows. In the processor-verification case study from Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing, the authors state that RISC-V VP is a virtual prototype written in SystemC TLM and that it supports many RISC-V instruction sets.[1]

A separate public GitHub source, Xilinx/libsystemctlm-soc, describes itself as a SystemC/TLM-2.0 co-simulation framework.[2]

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RELATIONSHIPS

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Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 1e

The paper embeds the RTL-core and ISS into a common SystemC TLM testbench.

RISC-V VP ← uses 100% 1e

RISC-V VP is written in SystemC TLM.

LINKED ENTITIES

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RISC-V VP USES Extracted graph relationship

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] RISC-V VP is a virtual prototype written in SystemC TLM and supports many RISC-V instruction sets. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] The verification workflow translates the RTL core to C++ with Verilator and embeds it with the ISS into a common SystemC testbench. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] SystemC lacks functionality to reset the whole simulation including the scheduler, motivating use of the out-of-process fuzzer AFL 2.56b as a baseline in the cited study. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] Xilinx/libsystemctlm-soc is summarized as a SystemC/TLM-2.0 co-simulation framework. Xilinx/libsystemctlm-soc