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SystemC TLM

Tool WIKI v1 · 5/28/2026

SystemC TLM is used in the provided evidence as a modeling and co-simulation technology for virtual prototypes and processor-verification testbenches. The RISC-V VP reference model is described as a virtual prototype written in SystemC TLM, and a processor-verification study embeds a Verilated RTL core and the RISC-V VP ISS into a common SystemC testbench.

Overview

SystemC TLM appears in the provided evidence as the implementation technology for virtual-prototype and co-simulation workflows. In the processor-verification case study from Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing, the authors state that RISC-V VP is a virtual prototype written in SystemC TLM and that it supports many RISC-V instruction sets.[1]

A separate public GitHub source, Xilinx/libsystemctlm-soc, describes itself as a SystemC/TLM-2.0 co-simulation framework.[2]

Use in processor co-simulation

In the cited fuzzing-based verification workflow, the device under test is the open-source VexRiscv processor RTL. The authors use an instruction-set simulator extracted from RISC-V VP as the reference ISS. To enable co-simulation, they translate the RTL core to C++ with Verilator and embed it together with the ISS into a common SystemC testbench.[1]

This positions SystemC TLM in the workflow as part of a cross-level verification setup: an RTL implementation and a reference ISS execute in a shared SystemC-based co-simulation environment, enabling mismatches to be detected during fuzzing-driven processor verification.[1]

Practical constraint noted in the evidence

The paper notes a SystemC-specific limitation relevant to fuzzing: SystemC has no functionality to reset the whole simulation, including the scheduler. Because of that limitation, the authors used the out-of-process fuzzer AFL 2.56b as their baseline.[1]

Related projects and literature

  • RISC-V VP: described in the evidence as a virtual prototype written in SystemC TLM and used as the source of the reference ISS in the processor-verification case study.[1]
  • Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing: uses a SystemC-based co-simulation setup in which a Verilated RTL core and an ISS from RISC-V VP are embedded into a common SystemC testbench.[1]
  • Xilinx/libsystemctlm-soc: a public GitHub project summarized as a SystemC/TLM-2.0 co-simulation framework.[2]

References

[1] Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing, evidence chunk c633ebdf-6fe4-49e1-bcdf-c2a01e52af3d.

[2] GitHub public context: Xilinx/libsystemctlm-soc, https://github.com/Xilinx/libsystemctlm-soc.

LINKED ENTITIES

2 links
RISC-V VP USES
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing USES

CITATIONS

4 sources
4 citations
[1] RISC-V VP is a virtual prototype written in SystemC TLM and supports many RISC-V instruction sets. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] The verification workflow translates the RTL core to C++ with Verilator and embeds it with the ISS into a common SystemC testbench. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] SystemC lacks functionality to reset the whole simulation including the scheduler, motivating use of the out-of-process fuzzer AFL 2.56b as a baseline in the cited study. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] Xilinx/libsystemctlm-soc is summarized as a SystemC/TLM-2.0 co-simulation framework. Xilinx/libsystemctlm-soc