Overview

RISC-V VP (riscv-vp) is a RISC-V virtual-prototype tool with a public repository identified in verification literature as https://github.com/agra-uni-bremen/riscv-vp. [RISC-V VP repository]

The provided evidence specifically documents the tool through its RISC-V VP ISS in processor-verification experiments. In a coverage-guided fuzzing study, VexRiscv behavior was compared against the RISC-V VP ISS, and the paper describes the VP decoder in that context as an RV32IM decoder that did not support the compressed-instruction extension RV32C. [RISC-V VP ISS and decoder]

Verification-related use

RISC-V VP appears in evidence associated with cross-level RISC-V processor verification. The DATE 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging cites the riscv-vp repository in its tool context, alongside Verilator. [RISC-V VP repository]

In a related coverage-guided fuzzing study, the RISC-V VP ISS served as the comparison point for VexRiscv behavior. The reported findings include CSR-related discrepancies around counter CSRs and trap-handling CSRs such as mepc and mtval; the paper also notes that many counter-CSR value discrepancies were not bugs, but reflected different micro-architectural details. [CSR comparison findings]

Compressed-instruction mtval mismatch

One documented mismatch involved compressed instructions. When VexRiscv executed a compressed instruction, the core raised an illegal-instruction fault and placed the 16-bit compressed instruction into mtval. The RISC-V VP ISS instead placed the decoded 32-bit instruction into mtval, because the VP RV32IM decoder did not support RV32C. The paper states that the RISC-V specification was unclear at that point. [Compressed instruction mtval mismatch]

Successor project

Public repository context identifies RISCV-VP++ as an extended and improved successor of the RISC-V VP virtual prototype. That successor is described as a C++ project maintained at the Institute for Complex Systems, Johannes Kepler University Linz. [RISCV-VP++ successor]

Evidence-backed characterization

• RISC-V virtual-prototype / ISS tooling associated with the agra-uni-bremen/riscv-vp repository. [RISC-V VP repository]
• Used as an ISS comparison point in RISC-V processor-verification research. [CSR comparison findings]
• Documented RV32IM decoder behavior did not support RV32C in the cited compressed-instruction mismatch. [RISC-V VP ISS and decoder]
• Succeeded by RISCV-VP++, according to public repository context. [RISCV-VP++ successor]