RVVTS

Tool

First seen 6/10/2026

Last seen 9/5/2026

Evidence 35 chunks

NEIGHBORHOOD

24 nodes · 47 edges

graph · RVVTS · depth=1

RELATIONSHIPS

50 connections

Functional Coverage uses → 100% 4e

RVVTS performs functional coverage measurement as part of its verification flow.

FP-RVVTS ← extends 100% 4e

FP-RVVTS is an enhanced version of RVVTS extended with FP support.

Machine State uses → 100% 4e

RVVTS uses Machine State data structures to represent and compare architectural states.

riscv-ovpsim uses → 100% 3e

RVVTS uses riscvOVPsim as the functional coverage metric tool.

spike uses → 100% 3e

RVVTS uses Spike as the reference simulator for co-simulation and architectural state comparison.

RISC-V Vector extension evaluates → 100% 2e

RVVTS is specifically designed to test and evaluate RVV implementations

instruction validity checking evaluates → 90% 2e

RVVTS evaluates instruction validity checking through negative testing

From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV ← uses 100% 2e

The paper extends and uses the RVVTS framework for RTL verification of RVV.

coverage-guided test generation implements → 100% 2e

RVVTS combines coverage-guided test generation with single-instruction isolation.

single-instruction isolation implements → 100% 2e

RVVTS implements single-instruction isolation to isolate failing instructions.

RefCovRunner ← part of 100% 2e

RefCovRunner is a Runner component of RVVTS that provides Machine State and functional coverage values.

RISC-V VP uses → 100% 2e

RVVTS applies test sets on RISC-V VP++ as a DUT.

QEMU uses → 100% 2e

RVVTS applies test sets on QEMU as a DUT.

RISC-V targets ISA → 95% 2e

RVVTS targets the RISC-V ISA in both RV32 and RV64 configurations.

single-instruction isolation uses → 100% 2e

RVVTS uses single instruction isolation for failure analysis

AraRunner ← part of 100% 2e

AraRunner is a component within the RVVTS framework that serves as the Execution Runner for Ara.

Valid Sequences test set uses → 100% 2e

RVVTS generates Valid Sequences test sets targeting pure positive testing.

Invalid+Valid Sequences test set uses → 100% 2e

RVVTS generates Invalid+Valid Sequences test sets targeting positive/negative testing.

RTL verification uses → 100% 2e

RVVTS is extended to support RTL verification, enabling application to RVV RTL implementations.

Jupyter notebooks uses → 95% 2e

RVVTS supports integration with Jupyter notebooks for interactive use.

Single instruction isolation for RISC-V vector test failures ← introduces 100% 2e

The paper introduces the RVVTS framework.

RISC-V Vector Tests Generator ← compares with 100% 2e

RVVTS is compared against the RISC-V Vector Tests Generator, achieving significantly higher functional coverage.

single-instruction isolation implements → 95% 2e

RVVTS implements single-instruction isolation for test failures.

Coverage-Guided Test Generation implements → 95% 2e

RVVTS implements coverage-guided test set generation through the CovGuidedTestsetGenerator.

Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← uses 100% 2e

The paper uses RVVTS as automated testing framework to compare Sail-RISC-V against Spike

Coverage-Guided Test Generation uses → 100% 2e

RVVTS uses coverage-guided test generation for positive and negative testing

QEMU evaluates → 90% 1e

RVVTS uncovered bugs in QEMU during its evaluation.

Verilator uses → 90% 1e

RVVTS uses Verilator to simulate the Ara RTL model.

invalid instruction sequences uses → 100% 1e

RVVTS generates invalid instruction sequences for negative testing

Negative Testing implements → 100% 1e

RVVTS is a framework for positive and negative testing.

positive testing implements → 100% 1e

RVVTS is a framework for positive and negative testing.

Single Instruction Isolation with Code Minimization implements → 100% 1e

RVVTS implements the Single Instruction Isolation with Code Minimization technique via the CodeErrMinRunner.

grammar-based ISG implements → 100% 1e

RVVTS comes with a grammar-based ISG for RV32 and RV64 configurations.

RISC-V Vector Extension (RVV) evaluates → 100% 1e

RVVTS is designed to evaluate RVV implementations.

Code Fragment uses → 100% 1e

RVVTS uses Code Fragments to organize assembler code.

Code Block uses → 100% 1e

RVVTS uses Code Blocks to organize sequences of Code Fragments.

CodeErrMinRunner ← part of 100% 1e

CodeErrMinRunner is a component of the RVVTS framework.

CodeCompareRunner ← part of 100% 1e

CodeCompareRunner is a component of the RVVTS framework used to detect deviations.

TestsetCodeErrMinRunner ← part of 100% 1e

TestsetCodeErrMinRunner is a variant Runner in the RVVTS framework for running pre-generated test sets.

GDBRunner ← part of 100% 1e

GDBRunner is a Runner component of RVVTS for connecting to targets via GDB protocol.

RISC-V Vector Extension (RVV) targets ISA → 100% 1e

RVVTS targets the RISC-V Vector Extension (RVV) for testing.

failure code minimization uses → 100% 1e

RVVTS uses failure code minimization to produce minimal failing test cases

positive testing uses → 100% 1e

RVVTS generates test sets for positive testing

Negative Testing uses → 100% 1e

RVVTS generates test sets for negative testing

Functional Coverage evaluates → 100% 1e

RVVTS measures functional coverage of RVV instructions

Machine State evaluates → 100% 1e

RVVTS compares resulting machine states to detect deviations

valid instruction sequences uses → 100% 1e

RVVTS generates valid instruction sequences for positive testing

positive and negative testing implements → 100% 1e

RVVTS is a framework for positive and negative testing of RISC-V vector instructions.

sail-riscv evaluates → 100% 1e

RVVTS is used to evaluate Sail-RISC-V as a Design Under Test

saturation flag evaluates → 90% 1e

RVVTS detects deviations related to saturation flag behavior