riscv-ovpsim
Toolriscv-ovpsim is the Imperas-developed open-source RISC-V instruction set simulator (ISS) family that includes the free riscvOVPsim compliance simulator and the extended riscvOVPsimPlus reference model. It is published on GitHub under the riscv-ovpsim organization and is widely used as a reference model for RISC-V processor verification, supporting multiple ratified ISA extensions and additional advanced features.
First seen 5/25/2026
Last seen 9/5/2026
Evidence 28 chunks
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WIKI
riscv-ovpsim
Overview
riscv-ovpsim is the GitHub organization / project line maintained by Imperas that distributes the RISC-V instruction set simulators (ISS) used as free reference models for RISC-V processor design verification. The family includes the freely available riscvOVPsim compliance simulator and the extended riscvOVPsimPlus reference model, both of which are based on Imperas's OVP (Open Virtual Platform) simulation infrastructure.
NEIGHBORHOOD
6 nodes · 9 edgesgraph · riscv-ovpsim · depth=1
RELATIONSHIPS
19 connectionsRISCV-DV supports co-simulation with riscv-ovpsim.
FP-RVVTS uses riscvOVPSim for functional coverage measurement during test-set generation.
RVVTS uses riscvOVPsim as the functional coverage metric tool.
riscvOVPsim is from Imperas and is the official reference simulator for compliance testing.
The paper evaluates riscvOVPsim and finds bugs in it.
Imperas Vector Test Suite uses riscvOVPsim as its ISS and coverage tool.
riscvOVPsim is a RISC-V instruction set simulator used as the reference for compliance testing.
riscv-ovpsim is authored by Imperas, as indicated by the tool name and its association with the imperas-riscv-tests project.
run.py can invoke riscv-ovpsim for ISS simulation
RefCovRunner uses riscvOVPsim for functional coverage measurement.
riscvOVPsim is developed and provided by Imperas.
FORCE-RISCV uses riscvOVPsim as its coverage tool.
riscvOVPsim is used to measure functional coverage for the RISC-V Vector Tests Generator evaluation.
Co-simulation in RISCV-DV uses riscv-ovpsim as one of the supported ISS tools.
The paper evaluates the complete CT infrastructure on riscvOVPsim.
riscvOVPsim is used as the compliance simulator for RISC-V architectural tests.
riscvOVPsimPlus extends the functionality of riscvOVPsim with additional features.
Imperas provides the free riscvOVPsim compliance simulator for RISC-V.
The imperas-riscv-tests repository is associated with the riscv-ovpsim GitHub organization, indicating it is part of the riscv-ovpsim toolset.
CITATIONS
9 sources9 citations — click to expand
[1] riscv-ovpsim is the Imperas-developed line of RISC-V ISS reference models, including the free riscvOVPsim compliance simulator and riscvOVPsimPlus reference model, hosted under the riscv-ovpsim GitHub organization. RISC-V Verification: The 5 Levels of Simulation-based Processor Hardware DV
[2] riscvOVPsimPlus extends riscvOVPsim with fully configurable instruction trace, GDB/Eclipse debug, memory configuration options, CLIC, Debug Module/Mode, multi-hart, H-hypervisor simulation, and ISA extensions V-vector, B-bitmanip, K-crypto (scalar), Zfinx, plus near-ratified P-SIMD/DSP and Zmmul. Survey of Verification of RISC-V Processors
[3] riscvOVPsim supports all standard ratified RISC-V extensions and is used as a free reference model for simple basic architectural validation testing. RISC-V Verification: The 5 Levels of Simulation-based Processor Hardware DV
[4] In the trace-compare verification flow, an ISG generates random but legal instruction sequences applied to both RTL and ISS, with trace log files compared instruction by instruction across PC, CSRs, GPRs, and internal state. Survey of Verification of RISC-V Processors
[5] Google's RISCV-DV instruction stream generator supports co-simulation with multiple ISS implementations including riscv-ovpsim. hw/top_matcha/ip/smc/vendor/google_riscv-dv - hw/matcha - Git at Google
[6] riscvOVPsim was one of the RISC-V simulators (alongside SPIKE, VP, GRIFT, SAIL) evaluated in mutation-based compliance testing for the base RV32I ISA. Mutation-based Compliance Testing for RISC-V
[7] In FP-RVVTS floating-point testing research, riscvOVPsim was used measuring only the F and D extensions of RISC-V when comparing against other simulators. FP-RVVTS floating-point RISC-V testing paper
[8] The GitHub repository riscv-ovpsim/imperas-riscv-tests is written primarily in C and reported 201 stars and 40 forks as of 2026-05-20. riscv-ovpsim/imperas-riscv-tests GitHub repository metadata
[9] A Gitee mirror of imperas-riscv-tests exists under user fjwei, tagged v20230724, described as a 20230830 mirror of the upstream riscv-ovpsim/imperas-riscv-tests repository, and does not specify a license. imperas-riscv-tests Gitee mirror