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riscv-ovpsim

Tool WIKI v2 · 7/9/2026

riscv-ovpsim is the Imperas-developed open-source RISC-V instruction set simulator (ISS) family that includes the free riscvOVPsim compliance simulator and the extended riscvOVPsimPlus reference model. It is published on GitHub under the riscv-ovpsim organization and is widely used as a reference model for RISC-V processor verification, supporting multiple ratified ISA extensions and additional advanced features.

riscv-ovpsim

Overview

riscv-ovpsim is the GitHub organization / project line maintained by Imperas that distributes the RISC-V instruction set simulators (ISS) used as free reference models for RISC-V processor design verification. The family includes the freely available riscvOVPsim compliance simulator and the extended riscvOVPsimPlus reference model, both of which are based on Imperas's OVP (Open Virtual Platform) simulation infrastructure.

The associated GitHub repository riscv-ovpsim/imperas-riscv-tests is written primarily in C and is used as a repository of RISC-V test programs paired with the simulator [chunk: 23fd1557-b2ac-4168-b6af-d1445f1a1d18; a2405b2a-182f-437d-98b3-f2b642af6917].

Purpose and role in RISC-V verification

riscvOVPsim is provided free of charge by Imperas to support basic RISC-V architectural conformance validation. It supports all of the standard ratified RISC-V extensions and can be used for simple tests of basic architectural compliance [chunk: a2405b2a-182f-437d-98b3-f2b642af6917].

riscvOVPsimPlus extends riscvOVPsim with additional functionality required for use as a full verification reference model. Documented extensions include [chunk: 23fd1557-b2ac-4168-b6af-d1445f1a1d18]:

  • Fully configurable instruction trace
  • GDB/Eclipse debug support
  • Memory configuration options
  • CLIC (Core-Local Interrupt Controller) support
  • Debug Module / Debug Mode support
  • Multi-hart simulation
  • H-hypervisor simulation
  • Recently ratified ISA extensions: V-vector, B-bitmanip, K-crypto (scalar), and Zfinx
  • 'Near-ratified' extensions: P-SIMD/DSP and Zmmul

riscvOVPsimPlus also supports both configuration options and version references for the underlying RISC-V specifications, covering the full envelope of verification reference model requirements [chunk: a2405b2a-182f-437d-98b3-f2b642af6917].

Verification flows in which riscv-ovpsim is used

Simple log / signature comparison (Stage 1)

A simple verification flow applies the RISC-V international architectural compliance test suites, which are configured as tests with an integrated signature indicating pass. The reference simulator riscvOVPsim (available free from GitHub) is used in this flow. Because it supports all standard ratified RISC-V extensions, it can be used for simple basic architectural validation testing [chunk: 54ea4c86-3ed8-4a43-8ed1-d3aff6b3ffaf; a2405b2a-182f-437d-98b3-f2b642af6917].

Post-simulation trace-compare (Stage 2)

In the trace-based design verification flow, an Instruction Stream Generator (ISG) generates random but legal RISC-V instruction sequences, which are applied to both the RTL under test and the ISS in reference mode. Separate trace log files are written by each and run through a compare program to observe differences or failures. Imperas provides the free reference model riscvOVPsimPlus to support this trace-based flow [chunk: 54ea4c86-3ed8-4a43-8ed1-d3aff6b3ffaf; 23fd1557-b2ac-4168-b6af-d1445f1a1d18; a2405b2a-182f-437d-98b3-f2b642af6917].

The compare step inspects the program counter (PC), Control and Status Registers (CSRs), General Purpose Registers (GPRs), and other internal state, instruction by instruction, examining execution flow, program data, and programmers' / internal state. This immediate comparison allows direct debug examination at the point of failure. The approach has been used on CV32E40P in OpenHW 1H 2020 [chunk: 23fd1557-b2ac-4168-b6af-d1445f1a1d18].

The trace-compare method has efficiency limitations: trace files can become very large, and discrepancies may occur early in the test, making the method suitable mainly for simple processors. It also does not work for asynchronous events, control flow effects, or hardware real-time effects [chunk: 23fd1557-b2ac-4168-b6af-d1445f1a1d18; a2405b2a-182f-437d-98b3-f2b642af6917].

Use as a co-simulation ISS

Google's RISCV-DV (riscv-dv) instruction stream generator supports co-simulation with multiple ISS implementations, including spike, riscv-ovpsim, whisper, and sail-riscv [chunk: 3bb5e1c5-98cd-40eb-80c1-a6b331968f8e].

Use in compliance and floating-point testing research

riscvOVPsim is one of the RISC-V simulators evaluated in mutation-based compliance testing research, alongside SPIKE, VP, GRIFT, and SAIL [chunk: e125a551-dae2-4884-9f3a-d65c5b0886b2].

In floating-point testing research, riscvOVPsim is used to measure only the F and D floating-point extensions of RISC-V when comparing against other simulators such as Spike and QEMU [chunk: 8f484457-517e-4cc4-a99d-662e2fa502d8].

Repository status (public context)

The public repository metadata for riscv-ovpsim/imperas-riscv-tests reports [source: github metadata]:

A mirror of the same repository is also published on Gitee under the user fjwei, tagged v20230724, and described as a 20230830 mirror of the upstream GitHub repository. The Gitee mirror does not specify a license, and users are directed to consult the upstream project description and its upstream code dependencies [chunk: 9279c1af-696a-41c8-941c-0c3b364b6fe7].

Licensing

The Gitee mirror of imperas-riscv-tests does not specify a license; users are advised to verify licensing against the upstream project [chunk: 9279c1af-696a-41c8-941c-0c3b364b6fe7]. The upstream license terms for the riscv-ovpsim organization repositories are not explicitly captured in the provided evidence.

Related entities

  • imperas-riscv-tests — Part of the riscv-ovpsim project line; this is the associated RISC-V test suite repository under the same GitHub organization, used alongside the simulators for compliance and reference-model testing.
  • Imperas — Authored by / maintained by Imperas, the organization that develops and distributes the riscvOVPsim and riscvOVPsimPlus reference models.

LINKED ENTITIES

2 links
imperas-riscv-tests PART_OF
Imperas AUTHORED_BY

CITATIONS

9 sources
9 citations
[1] riscv-ovpsim is the Imperas-developed line of RISC-V ISS reference models, including the free riscvOVPsim compliance simulator and riscvOVPsimPlus reference model, hosted under the riscv-ovpsim GitHub organization. RISC-V Verification: The 5 Levels of Simulation-based Processor Hardware DV
[2] riscvOVPsimPlus extends riscvOVPsim with fully configurable instruction trace, GDB/Eclipse debug, memory configuration options, CLIC, Debug Module/Mode, multi-hart, H-hypervisor simulation, and ISA extensions V-vector, B-bitmanip, K-crypto (scalar), Zfinx, plus near-ratified P-SIMD/DSP and Zmmul. Survey of Verification of RISC-V Processors
[3] riscvOVPsim supports all standard ratified RISC-V extensions and is used as a free reference model for simple basic architectural validation testing. RISC-V Verification: The 5 Levels of Simulation-based Processor Hardware DV
[4] In the trace-compare verification flow, an ISG generates random but legal instruction sequences applied to both RTL and ISS, with trace log files compared instruction by instruction across PC, CSRs, GPRs, and internal state. Survey of Verification of RISC-V Processors
[5] Google's RISCV-DV instruction stream generator supports co-simulation with multiple ISS implementations including riscv-ovpsim. hw/top_matcha/ip/smc/vendor/google_riscv-dv - hw/matcha - Git at Google
[6] riscvOVPsim was one of the RISC-V simulators (alongside SPIKE, VP, GRIFT, SAIL) evaluated in mutation-based compliance testing for the base RV32I ISA. Mutation-based Compliance Testing for RISC-V
[7] In FP-RVVTS floating-point testing research, riscvOVPsim was used measuring only the F and D extensions of RISC-V when comparing against other simulators. FP-RVVTS floating-point RISC-V testing paper
[8] The GitHub repository riscv-ovpsim/imperas-riscv-tests is written primarily in C and reported 201 stars and 40 forks as of 2026-05-20. riscv-ovpsim/imperas-riscv-tests GitHub repository metadata
[9] A Gitee mirror of imperas-riscv-tests exists under user fjwei, tagged v20230724, described as a 20230830 mirror of the upstream riscv-ovpsim/imperas-riscv-tests repository, and does not specify a license. imperas-riscv-tests Gitee mirror

VERSION HISTORY

v2 · 7/9/2026 · minimax/minimax-m3 (current)
v1 · 5/25/2026 · gpt-5.5