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Closing the RISC-V compliance gap: Looking from the negative testing side

Paper

“Closing the RISC-V compliance gap: Looking from the negative testing side” is a DAC 2020 paper by Vladimir Herdt, Daniel Große, and Rolf Drechsler. The available evidence identifies it through the reference list of “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study,” where it appears as a cited work on RISC-V ISA compliance and negative testing.

First seen 5/30/2026
Last seen 5/30/2026
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Wiki v1

WIKI

Overview

“Closing the RISC-V compliance gap: Looking from the negative testing side” is a paper listed in the references of Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. The reference entry identifies the authors as V. Herdt, D. Große, and R. Drechsler, and states that the paper appeared in DAC, 2020.

The title indicates that the paper addresses the RISC-V compliance gap from the perspective of negative testing. The available evidence does not include the paper’s abstract, method details, evaluation, or conclusions, so those aspects cannot be summarized here without additional sources.

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections
The paper cites work on negative testing for RISC-V compliance.
Vladimir Herdt authored by → 95% 1e
Vladimir Herdt is an author of the negative testing paper.
Daniel Große authored by → 95% 1e
Daniel Große is an author of the negative testing paper.
Rolf Drechsler authored by → 95% 1e
Rolf Drechsler is an author of the negative testing paper.

CITATIONS

4 sources
4 citations — click to collapse
[1] The paper is titled “Closing the RISC-V compliance gap: Looking from the negative testing side.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The paper is authored by V. Herdt, D. Große, and R. Drechsler. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] The paper is cited in the reference list of “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study