Closing the RISC-V compliance gap: Looking from the negative testing side
Paper“Closing the RISC-V compliance gap: Looking from the negative testing side” is a DAC 2020 paper by Vladimir Herdt, Daniel Große, and Rolf Drechsler. The available evidence identifies it through the reference list of “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study,” where it appears as a cited work on RISC-V ISA compliance and negative testing.
First seen 5/30/2026
Last seen 8/7/2026
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Overview
“Closing the RISC-V compliance gap: Looking from the negative testing side” is a paper listed in the references of Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. The reference entry identifies the authors as V. Herdt, D. Große, and R. Drechsler, and states that the paper appeared in DAC, 2020.
The title indicates that the paper addresses the RISC-V compliance gap from the perspective of negative testing. The available evidence does not include the paper’s abstract, method details, evaluation, or conclusions, so those aspects cannot be summarized here without additional sources.
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48 connectionsThe paper is authored by Vladimir Herdt.
The paper is authored by Rolf Drechsler.
The paper is authored by Daniel Große.
The paper uses LLVM libFuzzer as the fuzzing engine.
The paper evaluates riscvOVPsim and finds bugs in it.
The paper evaluates Spike simulator for compliance testing.
The paper evaluates the RISC-V VP simulator for compliance testing.
The paper evaluates GRIFT simulator for compliance testing.
The paper evaluates sail-riscv simulator for compliance testing.
The paper incorporates a custom coverage metric to improve fuzzing effectiveness.
The paper incorporates a custom fuzzing mutator to improve test generation.
The paper uses a test-case template as RISC-V assembler source file for simulation.
The paper generates compliance signatures for comparison against reference outputs.
The paper uses a static analysis filter to drop bytestreams with infinite loops and platform-specific details.
The paper introduces a fuzzing-based test-suite generation approach for RISC-V compliance testing.
The paper leverages coverage-guided fuzzing techniques based on LLVM libFuzzer.
The paper uses Clang compiler instrumentation to enable coverage reporting to libFuzzer.
The paper uses the ISS of the RISC-V VP as the foundation for fuzzing.
The paper mentions the RISC-V Torture Test Generator as related work.
The paper mentions constraint solving as a technique used in related test generation approaches.
The paper discusses the challenge of compliance testing for the privileged ISA.
The paper discusses CSRs as a challenge for compliance testing.
The paper mentions RTL simulation as required by RISCV-DV.
The paper evaluates its approach on the RV32I ISA configuration.
The paper evaluates its approach on the RV32IMC ISA configuration.
The paper evaluates its approach on the RV32GC ISA configuration.
The paper mentions MicroTESK as a related test generation framework.
The paper mentions Bayesian network-based test generation as a related approach.
The paper mentions machine learning-based test generation as a related approach.
The paper mentions model checking as a formal verification approach for RISC-V.
Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← mentions 100% 1e
The paper cites the negative testing compliance gap paper
The paper mentions Genesys-Pro as a related test generation framework.
The paper mentions the negative testing approach from the related paper.
The paper is affiliated with DFKI GmbH.
The paper mentions Verilator as a tool used to compile RTL cores to C++ simulators.
This paper leverages coverage-guided fuzzing to generate compliance tests.
The paper mentions UVM as required by RISCV-DV.
The paper mentions ELF format as used by a related approach that is not compliance-testing compatible.
The paper uses structural and value coverage rules to strengthen positive testing.
The paper uses abstract local execution in the filter to traverse local control flow.
The paper cites work on negative testing for RISC-V compliance.
The paper mentions registering a trap handler as part of the test-case template.
The paper is affiliated with the University of Bremen.
The paper uses hash-based coverage as one of the additional coverage metrics.
The paper presents negative testing approach for RISC-V compliance
The paper mentions RISCV-DV as a related tool with limited negative testing support.
The paper mentions riscv-formal as a formal verification approach for RISC-V.
The paper mentions the OneSpin 360 DV RISC-V Verification App as a formal verification tool.
LINKED ENTITIES
4 linksCITATIONS
4 sources4 citations — click to collapse
[1] The paper is titled “Closing the RISC-V compliance gap: Looking from the negative testing side.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The paper is authored by V. Herdt, D. Große, and R. Drechsler. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[3] The paper appeared in DAC in 2020. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] The paper is cited in the reference list of “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study