Mutation-based Compliance Testing for RISC-V
PaperFirst seen 6/10/2026
Last seen 6/10/2026
Evidence 11 chunks
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36 connectionsThe paper leverages symbolic execution to generate test-cases that kill mutants.
The paper discusses CSRs as a future extension direction and in context of virtual memory.
The paper mentions ELF test files in the context of test execution infrastructure.
The paper addresses RISC-V compliance testing.
The paper evaluates the complete CT infrastructure on GRIFT and finds a bug.
The paper defines mutation classes tailored for RISC-V as part of its approach.
The paper evaluates the quality of the official Compliance Test-suite using mutation analysis.
The paper compares its approach against the specification-based CT from the related paper.
The paper focuses on the RISC-V base RV32I ISA.
The paper proposes a mutation-based approach to boost RISC-V compliance testing.
The paper mentions RISCV-DV by Google as a related test generation tool.
The paper mentions riscv-formal as a formal verification approach for RISC-V.
The paper mentions OneSpin 360 DV as a formal verification approach for RISC-V.
The paper mentions the Scala-based Torture Test generator.
The paper mentions Certitude from Synopsys as a commercial tool using functional qualification principles.
The paper references MicroTESK as a specification-based test program generator.
The paper references functional qualification as a concept used in mutation-based RTL validation.
The paper mentions coverage-directed test generation using Bayesian networks as a related technique.
The paper discusses difference-based testing as a future direction.
The paper discusses evaluating the generated test-suite on RISC-V RTL cores as future work.
The paper references a virtual prototype (VP) as one of the evaluated RISC-V simulators.
The paper mentions that the official CT monitors quality by leveraging functional coverage metrics.
The paper mentions model checking approaches for RISC-V verification.
The paper mentions coverage-guided fuzzing as used by a related compliance testing approach.
The paper mentions constrained-random test generation as used by RISCV-DV.
Vladimir Herdt is listed as an author of the paper.
The paper mentions UVM as used by RISCV-DV for test generation.
Sören Tempel is listed as an author of the paper.
Daniel Große is listed as an author of the paper.
Rolf Drechsler is listed as an author of the paper.
The paper uses angr as the symbolic execution backend.
The paper evaluates the complete CT infrastructure on riscvOVPsim.
The paper evaluates the complete CT infrastructure on SPIKE.
The paper evaluates the complete CT infrastructure on the SAIL RISC-V model.
The paper mentions the negative testing approach from the related paper.
The paper references the coverage-guided fuzzing paper for ISS verification.