RISC-V Torture Test Generator

Tool

RISC-V Torture Test Generator is represented in the available evidence as the “RISC-V Torture” test/generator baseline evaluated in the paper “Verifying Instruction Set Simulators using Coverage-guided Fuzzing.” In that evaluation, RISC-V Torture test sets of 1,000, 5,000, and 10,000 cases were compared with RISC-V ISA Tests and a coverage-guided fuzzing approach for RISC-V instruction-set-simulator verification.

First seen 5/26/2026

Last seen 6/22/2026

Evidence 19 chunks

Wiki v2

WIKI

Overview

RISC-V Torture Test Generator is identified in the available evidence through the “RISC-V Torture” rows of the evaluation table in the paper “Verifying Instruction Set Simulators using Coverage-guided Fuzzing.” The table categorizes these rows under “Tests / Generator” and reports results for RISC-V Torture configurations of 1,000, 5,000, and 10,000 test cases.[C1]

The evidence does not describe the generator’s internal algorithm, input language, output format, repository, license, or supported RISC-V extensions. It supports only its use as an evaluated RISC-V test/generator baseline in the paper’s RISC-V instruction-set-simulator verification study.[C1][C2]

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

11 connections

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← compares with 100% 2e

The paper compares its CGF approach against the RISC-V Torture test generator.

RISC-V uses → 90% 2e

RISC-V Torture Test Generator generates test cases for RISC-V processors.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← mentions 90% 2e

The paper mentions the RISC-V Torture Test Generator as a related but more limited tool.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← uses 100% 2e

The paper integrates RISC-V Torture Test Generator for comparison in the evaluation.

Randomized Test Generation uses → 90% 1e

The Torture Test Generator generates tests by integrating pre-defined randomized test-sequences.

Instruction Sequence uses → 90% 1e

The RISC-V Torture test generator generates valid instruction sequences.

Random Tests implements → 97% 1e

The RISC-V torture test generator creates a single random torture test for verifying RISC-V processors.

Instruction Set Simulator (ISS) uses → 95% 1e

The torture test generator compares test results with an ISA simulator to find differences.

EPEX: Processor Verification by Equivalent Program Execution ← mentions 100% 1e

The paper mentions RISC-V Torture Test Generator as a related model-based test generation approach.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← compares with 70% 1e

The paper mentions the RISC-V Torture Test Generator as a related tool for RISC-V verification.

Mutation-based Compliance Testing for RISC-V ← mentions 90% 1e

The paper mentions the Scala-based Torture Test generator.

LINKED ENTITIES

2 links

Verifying Instruction Set Simulators using Coverage-guided Fuzzing USES Extracted graph relationship

RISC-V USES Extracted graph relationship

CITATIONS

2 sources

2 citations — click to collapse

[1] The paper’s evaluation table lists RISC-V Torture as a Tests/Generator baseline with 1,000, 5,000, and 10,000 test-case configurations and reports time, coverage, and error-finding results for each. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[2] The case study concerns RISC-V ISS verification, builds a coverage-guided fuzzing approach on libFuzzer, verifies an RV32IMA ISS from a RISC-V virtual prototype, and uses Spike and Forvis as reference ISSs. Verifying Instruction Set Simulators using Coverage-guided Fuzzing