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EPEX: Processor Verification by Equivalent Program Execution

Paper
First seen 6/22/2026
Last seen 6/22/2026
Evidence 6 chunks

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RELATIONSHIPS

12 connections
EPEX introduces → 100% 2e
The paper introduces the EPEX tool for processor verification by equivalent program execution.
riscv-formal mentions → 100% 2e
The paper mentions riscv-formal as a related formal verification tool for RISC-V.
RISC-V Sail Model mentions → 90% 2e
The paper mentions the RISC-V Sail Model as a formal RISC-V ISA specification.
Compliance Test-suite uses → 95% 2e
The paper uses the compliance test suite in experiments for EPEX evaluation.
Dhrystone benchmark uses → 95% 2e
The paper uses the Dhrystone benchmark in experiments for EPEX evaluation.
riscv-dv mentions → 100% 1e
The paper mentions RISC-V DV as a related test generation approach.
RISC-V Torture Test Generator mentions → 100% 1e
The paper mentions RISC-V Torture Test Generator as a related model-based test generation approach.
Genesys-Pro mentions → 85% 1e
The paper mentions Genesys-Pro as a related test program generation tool.
Lucas Klemmer authored by → 100% 1e
Lucas Klemmer is an author of the EPEX paper.
Daniel Große authored by → 100% 1e
Daniel Große is an author of the EPEX paper.
Symbolic Quick Error Detection ← compares with 95% 1e
The paper compares EPEX with Symbolic Quick Error Detection as a related formal verification approach.
OneSpin 360 DV mentions → 100% 1e
The paper mentions OneSpin 360 DV as a related commercial formal verification tool for RISC-V.