riscv-formal

Tool

riscv-formal is referenced in RISC-V verification literature as a RISC-V formal verification framework and as a notable model-checking-based formal verification approach.

First seen 5/26/2026

Last seen 6/7/2026

Evidence 10 chunks

Wiki v1

WIKI

Overview

riscv-formal is a tool/framework in the RISC-V verification ecosystem. A 2020 paper on cross-level processor verification for RISC-V identifies riscv-formal as a notable formal verification approach that leverages model checking, and its references list it as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.

Role in RISC-V verification

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NEIGHBORHOOD

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RELATIONSHIPS

14 connections

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 3e

The paper mentions riscv-formal as a notable formal verification approach for RISC-V.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← mentions 90% 2e

The paper mentions riscv-formal as a model checking-based verification tool.

Formal Property Checking via RVFI implements → 95% 1e

riscv-formal implements formal property checking via the RVFI interface.

RVFI-DII Interface uses → 90% 1e

riscv-formal uses the RVFI interface for formal property checking.

Model Checking implements → 95% 1e

riscv-formal leverages model checking for RISC-V verification.

ISA compliance verification implements → 99% 1e

riscv-formal is the framework used to perform ISA compliance verification of RISC-V processors

RVFI uses → 98% 1e

riscv-formal uses the RVFI interface as its standard wrapper interface for formal checks

Bounded Model Check uses → 97% 1e

riscv-formal supports setting up tests as bounded model checks

unbounded verification uses → 97% 1e

riscv-formal supports unbounded verification tasks in addition to bounded model checks

genchecks.py uses → 98% 1e

riscv-formal relies on genchecks.py to generate formal check configurations

smtbmc uses → 90% 1e

riscv-formal uses smtbmc as the engine for certain solver tasks such as outputting SMT2 traces

boolector uses → 97% 1e

riscv-formal defaults to boolector as its solver

RISC-V evaluates → 97% 1e

riscv-formal evaluates RISC-V processor implementations for ISA compliance

Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms ← evaluates 90% 1e

The paper discusses riscv-formal as a formal property checking framework.

CITATIONS

5 sources

5 citations — click to expand

[1] riscv-formal is identified as a notable RISC-V formal verification approach leveraging model checking.

[2] riscv-formal is referenced as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.

[3] Formal methods can provide correctness guarantees, but are more difficult to apply than simulation-based methods and may have complexity and scalability issues.

[4] The RISC-V ISA includes mandatory base integer instruction sets such as RV32I, RV64I, and RV128I, plus optional extensions such as M and C.

[5] The RISC-V privileged architecture includes execution modes, including mandatory Machine mode, and Control and Status Registers used for environment interaction, operating-system execution, and trap handling.