riscv-formal
Toolriscv-formal is referenced in RISC-V verification literature as a RISC-V formal verification framework and as a notable model-checking-based formal verification approach.
First seen 5/26/2026
Last seen 8/7/2026
Evidence 31 chunks
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WIKI
Overview
riscv-formal is a tool/framework in the RISC-V verification ecosystem. A 2020 paper on cross-level processor verification for RISC-V identifies riscv-formal as a notable formal verification approach that leverages model checking, and its references list it as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.
Role in RISC-V verification
NEIGHBORHOOD
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49 connectionsriscv-formal is a framework for performing formal verification of RISC-V cores.
The paper mentions riscv-formal as a notable formal verification approach for RISC-V.
The paper discusses riscv-formal as a related formal verification approach and compares it to its own methodology.
RVFI is part of the riscv-formal framework and is used for formal verification of RISC-V processors.
The paper mentions riscv-formal as a related formal verification tool for RISC-V.
genchecks.py is a tool within riscv-formal used to automatically generate testbench macros and checks.
EPEX is compared with riscv-formal as both target RISC-V processor verification.
The paper mentions riscv-formal as a model checking-based verification tool.
riscv-formal uses RVFI as its interface for connecting CSRs and retired instruction data.
riscv-formal uses the RVFI interface for formal property checking.
riscv-formal leverages model checking for RISC-V verification.
riscv-formal is the framework used to perform ISA compliance verification of RISC-V processors
riscv-formal supports setting up tests as bounded model checks
riscv-formal supports unbounded verification tasks in addition to bounded model checks
riscv-formal uses smtbmc as the engine for certain solver tasks such as outputting SMT2 traces
riscv-formal defaults to boolector as its solver
riscv-formal evaluates RISC-V processor implementations for ISA compliance
riscv-formal is used to perform formal verification by checking instructions one by one.
riscv-formal uses SystemVerilog/Verilog for instruction-level formal checks.
riscv-formal applies a Bounded Model Checking approach for RISC-V processor verification.
riscv-formal is a formal verification framework for RISC-V processors.
riscv-formal is maintained by YosysHQ.
riscv-formal requires rvfi_macros.vh to be the first verilog file read after defining configuration macros.
riscv-formal supports bounded model checking via the RISCV_FORMAL_CHECK_CYCLE macro.
riscv-formal supports unbounded model checking via the RISCV_FORMAL_UNBOUNDED macro.
riscv-formal supports liveness checks with fairness guarantees.
riscv-formal supports black-boxing the register file during instruction checks.
riscv-formal supports black-boxing the ALU during consistency checks.
riscv-formal supports verifying CSRs through the RVFI interface using dedicated macros.
riscv-formal provides configuration for cores that only support word-aligned memory access.
riscv-formal supports PMA configuration via the RISCV_FORMAL_PMA_MAP macro.
riscv-formal provides configuration macros to handle WFI and WFI-like wait instructions.
riscv-formal supports U-mode verification via the RISCV_FORMAL_UMODE macro.
riscv-formal supports S-mode verification via the RISCV_FORMAL_SMODE macro.
riscv-formal supports the RISC-V Compressed ISA via the RISCV_FORMAL_COMPRESSED macro.
riscv-formal accommodates fused instructions through the ILEN configuration macro.
riscv-formal includes assume_stmts.vh in the testbench when RISCV_FORMAL_ASSUME is defined.
riscv-formal uses the rvformal_rand_reg macro to declare random registers for formal and simulation contexts.
riscv-formal uses the rvformal_rand_const_reg macro to declare random constant registers for formal and simulation contexts.
riscv-formal supports Yosys as a formal verification backend.
riscv-formal targets RISC-V processor cores for formal verification.
The paper mentions riscv-formal as a formal verification approach for RISC-V.
riscv-formal is a formal verification approach for RISC-V based on model checking.
riscv-formal applies a Bounded Model Checking approach for RISC-V processor verification.
MicroRV32 was also verified using the riscv-formal tool.
The paper mentions riscv-formal as a formal verification approach for RISC-V.
Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms ← evaluates 90% 1e
The paper discusses riscv-formal as a formal property checking framework.
riscv-formal leverages model checking for RISC-V verification.
riscv-formal implements formal property checking via the RVFI interface.
CITATIONS
5 sources5 citations — click to expand
[1] riscv-formal is identified as a notable RISC-V formal verification approach leveraging model checking.
[2] riscv-formal is referenced as the “RISC-V formal verification framework” at https://github.com/SymbioticEDA/riscv-formal.
[3] Formal methods can provide correctness guarantees, but are more difficult to apply than simulation-based methods and may have complexity and scalability issues.