Model Checking

Technique

Model checking is referenced in the provided evidence as a formal technique used in some RISC-V processor-verification approaches. The evidence also notes that such formal techniques may be susceptible to scalability issues.

First seen 5/25/2026

Last seen 8/1/2026

Evidence 19 chunks

Wiki v1

WIKI

Overview

Model checking appears in the provided evidence as the basis for a few formal approaches in the RISC-V domain. These approaches are discussed alongside other processor-verification techniques such as directed test suites, simulation-based instruction-sequence generation, constraint-based specifications, fuzzing, and cross-level co-simulation.

Use in processor verification

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

15 connections

SMV model checker uses → 100% 2e

Model checking is performed using the SMV model checker tool

Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV ← uses 100% 2e

The paper applies model checking to generate functional test programs

functional test program generation ← uses 100% 2e

The functional test program generation approach uses model checking to generate test programs

SMV uses → 90% 1e

SMV is an existing model checker used with SystemC for formal verification.

SystemC uses → 90% 1e

SystemC is used to create formal models for model checking verification.

Pre-Silicon Verification ← uses 93% 1e

Model checking is used as a fully-automatic approach for pre-silicon formal verification.

Bounded Model Checking ← compares with 88% 1e

Model Checking is contrasted with Bounded Model Checking in the context of RISC-V security verification.

Formal Verification ← uses 92% 1e

Model checking is used as part of formal verification methodology.

A Methodology for Validation of Microprocessors using Equivalence Checking ← mentions 95% 1e

The paper mentions model checking as a related technique for processor verification.

Symbiotic Verification of RISC-V Processors ← uses 97% 1e

The paper combines symbolic execution with model checking for RISC-V verification.

Simulation-Based Verification compares with → 90% 1e

Model checking is presented as a formal alternative to simulation

riscv-formal ← implements 95% 1e

riscv-formal leverages model checking for RISC-V verification.

formal verification implements → 100% 1e

Model checking is a formal verification technique

OneSpin 360 DV RISC-V Verification App ← implements 95% 1e

OneSpin 360 DV RISC-V Verification App leverages model checking for RISC-V verification.

JasperGold uses → 94% 1e

Model checking formal verification is performed using the Jasper tool.

LINKED ENTITIES

1 links

Processor Verification USED_FOR Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] In the RISC-V domain, some formal approaches have been proposed that are based on model checking techniques. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] Formal techniques based on model checking may be susceptible to scalability issues. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] Model checking is used for processor verification in the RISC-V context. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing