Model Checking
TechniqueModel checking is referenced in the provided evidence as a formal technique used in some RISC-V processor-verification approaches. The evidence also notes that such formal techniques may be susceptible to scalability issues.
First seen 5/25/2026
Last seen 6/7/2026
Evidence 2 chunks
Wiki v1
WIKI
Overview
Model checking appears in the provided evidence as the basis for a few formal approaches in the RISC-V domain. These approaches are discussed alongside other processor-verification techniques such as directed test suites, simulation-based instruction-sequence generation, constraint-based specifications, fuzzing, and cross-level co-simulation.
Use in processor verification
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2 connectionsriscv-formal leverages model checking for RISC-V verification.
OneSpin 360 DV RISC-V Verification App leverages model checking for RISC-V verification.
LINKED ENTITIES
1 linksCITATIONS
3 sources3 citations — click to collapse
[1] In the RISC-V domain, some formal approaches have been proposed that are based on model checking techniques. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] Formal techniques based on model checking may be susceptible to scalability issues. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] Model checking is used for processor verification in the RISC-V context. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing