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JasperGold

Tool

JasperGold is cited in the RISC-V verification literature as a Cadence formal-verification tool used with RVFI tracing to prove equivalence between traces from a simple HDL model and a pipelined HDL implementation. The cited evidence notes practical limits for this approach: it handles only in-order pipelines, requires specialist knowledge, and does not yet replace functional testing for entire processors.

First seen 5/27/2026
Last seen 7/16/2026
Evidence 18 chunks
Wiki v1

WIKI

Overview

JasperGold is referenced as Cadence’s JasperGold in the context of RISC-V model-based formal verification. The cited work describes formal-verification tools for RISC-V as often using the RVFI tracing interface together with tools like JasperGold to prove that trace sequences from a simple HDL model are equivalent to trace sequences from a pipelined HDL implementation. [C1]

Role in RISC-V formal verification

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NEIGHBORHOOD

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RELATIONSHIPS

15 connections
RVFI uses → 100% 5e
JasperGold uses the RVFI tracing interface for formal verification.
Formal Verification ← uses 96% 3e
JasperGold is the formal verification platform used for property checking of RISC-V processors.
ENCARSIA ← uses 100% 2e
ENCARSIA uses JasperGold for formal verification of bug observability.
Encarsia ← uses 100% 2e
ENCARSIA uses JasperGold for formal verification of injected bugs.
formal verification implements → 95% 2e
JasperGold is a formal verification tool used for RISC-V pipeline verification.
Fine-Grained Code Analysis for Processor Fuzzing ← compares with 95% 1e
The paper compares its branch coverage results against JasperGold formal verification tool.
HyPFuzz ← uses 90% 1e
HyPFuzz integrates JasperGold as a formal tool to assist fuzzing.
Model Checking ← uses 94% 1e
Model checking formal verification is performed using the Jasper tool.
Property Checking ← uses 95% 1e
Property checking for CHERI-RISC-V is performed on the JasperGold platform.
Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification ← evaluates 95% 1e
The paper evaluates JasperGold for control logic transition coverage in RISC-V cores.
Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review ← uses 85% 1e
The review mentions JasperGold as part of the current RISC-V formal verification toolchain.
Model-Based Verification ← uses 90% 1e
JasperGold is used for formal verification of RISC-V implementations along with RVFI.
formal verification ← uses 90% 1e
Formal verification tools for RISC-V have used RVFI along with JasperGold.
Model-Based Formal Verification implements → 90% 1e
JasperGold is used for formal verification of RISC-V implementations using RVFI traces.
Cadence ← uses 90% 1e
JasperGold is a formal verification tool by Cadence used for RISC-V verification.

LINKED ENTITIES

2 links
formal verification IMPLEMENTS Extracted graph relationship
RVFI USES Extracted graph relationship

CITATIONS

2 sources
2 citations — click to collapse
[1] RISC-V formal-verification tools have often used the RVFI tracing interface along with tools like Cadence’s JasperGold to prove equivalence between trace sequences from a simple HDL model and a pipelined HDL implementation. Randomized Testing of RISC-V CPUs using Direct
[2] The cited formal-verification approach is limited to in-order pipelines, requires specialist knowledge, and does not yet replace functional testing for entire processors. Randomized Testing of RISC-V CPUs using Direct