RVFI

Concept

RVFI, the RISC-V Formal Interface, is used in the provided evidence as a per-instruction observation interface for RISC-V verification. TestRIG uses RVFI to observe architectural state changes after each instruction and compare execution traces between models, simulators, and simulated hardware implementations; RVFI-DII is used as a replay/interface context for TestRIG traces.

First seen 5/27/2026

Last seen 6/7/2026

Evidence 13 chunks

Wiki v2

WIKI

Overview

RVFI is identified in the evidence as the RISC-V Formal Interface standard. In TestRIG, RVFI is used to observe the change in state after each instruction of the RISC-V implementation under test. This makes RVFI a trace/reporting interface for comparing how an implementation behaves against a model or simulator at instruction granularity.

Role in TestRIG

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NEIGHBORHOOD

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RELATIONSHIPS

17 connections

TestRIG ← uses 100% 11e

TestRIG uses RVFI to observe execution traces from RISC-V implementations.

RVFI-DII ← extends 100% 5e

RVFI-DII extends RVFI with the Direct Instruction Injection input channel.

JasperGold ← uses 100% 5e

JasperGold uses the RVFI tracing interface for formal verification.

genchecks.py ← uses 97% 2e

genchecks.py generates checks that use the standard RVFI wrapper interface

Claire Wolf mentions → 100% 2e

RVFI was specified by Claire Wolf.

Formal Verification ← uses 95% 2e

Formal verification tools use RVFI as the tracing interface.

RVFI-DII ← uses 100% 1e

RVFI-DII uses RVFI as its trace output mechanism.

riscv-formal ← uses 98% 1e

riscv-formal uses the RVFI interface as its standard wrapper interface for formal checks

RVFI-DII extends → 100% 1e

RVFI-DII extends RVFI by adding Direct Instruction Injection capabilities.

rvfi_testbench.sv ← implements 95% 1e

rvfi_testbench.sv implements the RVFI testbench module

instruction check ← uses 95% 1e

Instruction checks test the instruction and state transitions as described by RVFI signals

PC check ← uses 95% 1e

PC checks use RVFI signals like rvfi_pc_wdata and rvfi_pc_rdata

causality check ← uses 93% 1e

Causality checks operate on the RVFI instruction stream

instruction memcheck ← uses 92% 1e

Instruction memcheck verifies that data from memory makes its way into rvfi_insn correctly

data memcheck ← uses 92% 1e

Data memcheck tests memory consistency as reported via RVFI signals

CSR check ← uses 95% 1e

CSR checks operate on RVFI signal ports to validate CSR behavior

faults check ← uses 93% 1e

Faults check uses RVFI signals including rvfi_mem_fault to verify fault handling

LINKED ENTITIES

3 links

TestRIG USES Extracted graph relationship

RVFI-DII EXTENDS Extracted graph relationship

JasperGold USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] RVFI is the RISC-V Formal Interface standard and TestRIG uses it to observe the change in state after each instruction of the implementation under test. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] TestRIG checks equivalence pragmatically by generating random instruction sequences, executing the same sequences on a model and implementation, and comparing execution traces; this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] Direct Instruction Injection supplies the next instruction from the test harness regardless of the CPU program counter, separate from RVFI's observation role. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] In the RISCV-DV evaluation flow, TestRIG traces are produced from Spike executing tests and replayed through RVFI-DII while measuring Sail RISC-V model coverage. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[5] TestRIG supports converting instruction traces to and from a human-readable format and using trace files as regression tests for previous counterexamples. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[6] The CIll public summary reports evaluation within the RISCV-Formal framework and notes that M-extension instructions are proved against the RVFI ALTOPS substitute semantics provided by RISCV-Formal. CIll: CTI-Guided Invariant Generation via LLMs for Model Checking