Formal Verification

Technique

In the provided evidence, formal verification is discussed in the context of RISC-V processor verification. The cited paper identifies formal verification approaches for RISC-V, including approaches that leverage model checking such as riscv-formal and the OneSpin RISC-V verification app, while positioning its own work as a test-generation and co-simulation approach rather than a formal method.

First seen 5/24/2026

Last seen 6/2/2026

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WIKI

Formal Verification

Formal verification is discussed in the provided evidence as a category of approaches used for RISC-V processor verification. The cited RISC-V processor-verification paper states that, in addition to test-generation methods, there are “a few formal verification approaches for RISC-V.” It identifies notable approaches that leverage model checking, including riscv-formal and the OneSpin 360 DV RISC-V Verification App. [C1]

Role in RISC-V verification

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 3e

The paper mentions formal verification approaches as complementary to simulation-based methods.

RVFI uses → 95% 2e

Formal verification tools use RVFI as the tracing interface.

SystemVerilog assertions uses → 93% 1e

Formal verification uses SystemVerilog assertions to express ISA-specified behavior.

JasperGold uses → 95% 1e

Formal verification tools for RISC-V have used JasperGold along with RVFI tracing.

Symbolic QED ← uses 85% 1e

Symbolic QED generates minimal tests for verification using a formal model of the pipeline.

pre-silicon verification mentions → 85% 1e

Formal verification is used in hardware pre-silicon verification but does not scale well.

Processor Verification ← uses 93% 1e

Formal verification is used to exhaustively explore input combinations against ISA-specified behavior.

LINKED ENTITIES

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Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study MENTIONS Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] The RISC-V processor-verification paper states that there are formal verification approaches for RISC-V and identifies model-checking-based approaches including riscv-formal and the OneSpin RISC-V verification app. Efficient Cross-Level Testing for

[2] The paper reports that its test-generation and co-simulation approach found several serious bugs in a pipelined industrial RISC-V TGF series core and processed more than 200 million instructions per hour. Efficient Cross-Level Testing for

[3] The paper’s references list a RISC-V formal verification framework, the OneSpin 360 DV RISC-V Verification App, and a formal specification of the RISC-V ISA in Kami. Efficient Cross-Level Testing for