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Formal Verification

Technique

In the provided evidence, formal verification is discussed in the context of RISC-V processor verification. The cited paper identifies formal verification approaches for RISC-V, including approaches that leverage model checking such as riscv-formal and the OneSpin RISC-V verification app, while positioning its own work as a test-generation and co-simulation approach rather than a formal method.

First seen 5/24/2026
Last seen 7/14/2026
Evidence 34 chunks
Wiki v3

WIKI

Formal Verification

Formal verification is discussed in the provided evidence as a category of approaches used for RISC-V processor verification. The cited RISC-V processor-verification paper states that, in addition to test-generation methods, there are “a few formal verification approaches for RISC-V.” It identifies notable approaches that leverage model checking, including riscv-formal and the OneSpin 360 DV RISC-V Verification App. [C1]

Role in RISC-V verification

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NEIGHBORHOOD

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RELATIONSHIPS

34 connections
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 3e
The paper mentions formal verification approaches as complementary to simulation-based methods.
RISC-V evaluates → 97% 3e
Formal verification is used to verify properties and correctness of RISC-V processors.
JasperGold uses → 96% 3e
JasperGold is the formal verification platform used for property checking of RISC-V processors.
Instruction Set Architecture evaluates → 93% 3e
Formal verification is used to verify the ISA specification compliance of processors.
Opcode Trojan evaluates → 94% 2e
Formal verification is used to detect opcode trojans in processor designs.
RVFI uses → 95% 2e
Formal verification tools use RVFI as the tracing interface.
Polynomial Formal Verification uses → 90% 2e
Polynomial Formal Verification is a specialized formal verification technique.
AI based SystemVerilog TB generation ← uses 90% 2e
The paper proposes combining formal verification with simulation-based approaches.
Functional Verification ← compares with 90% 2e
Formal verification is contrasted with simulation-based functional verification for exhaustiveness.
Property Checking uses → 93% 2e
Property checking is an integral part of the formal verification methodology.
Theorem Proving uses → 91% 2e
Theorem proving is used as part of formal verification for complete processor verification.
Processor Verification ← uses 97% 2e
Formal verification is used in processor verification to exhaustively verify sub-units and properties.
Assertion-Based Verification uses → 92% 2e
Assertions are used in formal verification to express and check design specifications.
hardware fuzzing compares with → 85% 1e
Hardware fuzzing is compared to formal verification as alternative techniques for detecting hardware vulnerabilities.
Processor Fuzzing compares with → 85% 1e
The paper compares formal verification and processor fuzzing as methods for RTL transient execution vulnerability detection.
Yosys uses → 93% 1e
Yosys is used as the formal verification framework for property and assumption checking.
riscv-formal uses → 95% 1e
riscv-formal is used to perform formal verification by checking instructions one by one.
Hardware fuzzing ← compares with 85% 1e
Formal Verification is contrasted with hardware fuzzing, being computationally intractable for full-scale designs.
Model Checking uses → 92% 1e
Model checking is used as part of formal verification methodology.
Bounded Model Checking uses → 80% 1e
Bounded model checking is mentioned as an alternative formal verification technique that may be used.
Binary Decision Diagram Verification uses → 88% 1e
BDD-based verification is used as part of polynomial formal verification of RISC-V.
HyPFuzz ← implements 100% 1e
HyPFuzz integrates formal verification tools to strengthen fuzzing.
Constraint-based Random Simulation ← compares with 87% 1e
The paper contrasts formal verification with simulation-based approaches, noting formal verification's limited capacity.
SystemVerilog assertions uses → 93% 1e
Formal verification uses SystemVerilog assertions to express ISA-specified behavior.
SystemVerilog ← implements 93% 1e
SystemVerilog assertions are used to capture ISA-specified behavior for formal verification.
pre-silicon verification mentions → 85% 1e
Formal verification is used in hardware pre-silicon verification but does not scale well.
RTL evaluates → 94% 1e
Formal verification is applied to RTL to detect architectural violations and bugs.
security verification evaluates → 88% 1e
Formal verification can expose security issues in processor implementations.
Axiomise ← uses 95% 1e
Axiomise uses formal verification for micro-architectural verification of RISC-V processors.
Symbolic QED ← uses 85% 1e
Symbolic QED generates minimal tests for verification using a formal model of the pipeline.
RISC-V Formal Framework ← implements 95% 1e
The RISC-V Formal Framework is an open-source tool for formal verification of RISC-V processors.
CV32E40P updates: customizing an open-source RISC-V core at industrial-grade ← uses 100% 1e
Formal Verification was analyzed and applied to verify Xpulp instructions.
Siemens EDA Onespin uses → 100% 1e
Siemens EDA Onespin tools were selected for formal verification.
RV32Xpulp ISA extension evaluates → 100% 1e
Formal Verification was applied to verify more than 300 Xpulp instructions.

LINKED ENTITIES

1 links
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study MENTIONS Extracted graph relationship

CITATIONS

3 sources
3 citations — click to collapse
[1] The RISC-V processor-verification paper states that there are formal verification approaches for RISC-V and identifies model-checking-based approaches including riscv-formal and the OneSpin RISC-V verification app. Efficient Cross-Level Testing for
[2] The paper reports that its test-generation and co-simulation approach found several serious bugs in a pipelined industrial RISC-V TGF series core and processed more than 200 million instructions per hour. Efficient Cross-Level Testing for
[3] The paper’s references list a RISC-V formal verification framework, the OneSpin 360 DV RISC-V Verification App, and a formal specification of the RISC-V ISA in Kami. Efficient Cross-Level Testing for