Formal Verification

Formal verification is discussed in the provided evidence as a category of approaches used for RISC-V processor verification. The cited RISC-V processor-verification paper states that, in addition to test-generation methods, there are “a few formal verification approaches for RISC-V.” It identifies notable approaches that leverage model checking, including riscv-formal and the OneSpin 360 DV RISC-V Verification App. [C1]

Role in RISC-V verification

The evidence places formal verification alongside other RISC-V verification activities, particularly test generation and co-simulation. The same paper contrasts its own on-the-fly instruction-stream generation and co-simulation approach with existing verification methods, reporting that its method processed more than 200 million instructions per hour and found several serious bugs in a pipelined industrial RISC-V TGF series core. [C2]

Related RISC-V formal artifacts

The paper’s references list several RISC-V-related formal resources, including the RISC-V formal verification framework at SymbioticEDA/riscv-formal, the OneSpin 360 DV RISC-V Verification App, and a formal specification of the RISC-V ISA in Kami. [C3]

Scope of the available evidence

The available evidence supports only a RISC-V-specific view of formal verification. It does not provide a general definition of formal verification, nor does it substantiate broader claims about formal methods outside the RISC-V processor-verification context.