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CV32E40P updates: customizing an open-source RISC-V core at industrial-grade

Paper
First seen 7/12/2026
Last seen 7/12/2026
Evidence 2 chunks

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RELATIONSHIPS

10 connections
RV32Xpulp ISA extension evaluates → 100% 2e
The paper presents verification of the RV32Xpulp ISA extension.
openhwgroup authored by → 100% 1e
The paper is co-authored by Pasquale Davide Schiavone and Mike Thompson from OpenHW Group.
CV32E40P evaluates → 100% 1e
The paper presents the verification project applied to the CV32E40P core.
step&compare uses → 95% 1e
The paper describes step&compare as a key verification technique applied to the core.
Universal Verification Methodology uses → 95% 1e
The paper describes the use of UVM in the verification environment.
Dolphin Design authored by → 100% 1e
The paper is authored by members of Dolphin Design and OpenHW Group.
ImperasDV uses → 100% 1e
The paper describes adoption of ImperasDV as the reference model.
Formal Verification uses → 100% 1e
Formal Verification was analyzed and applied to verify Xpulp instructions.
Siemens EDA Onespin uses → 100% 1e
Siemens EDA Onespin tools were selected for formal verification.
Core-V-Verif uses → 100% 1e
The paper describes reuse of Core-V-Verif for verification.