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STIMSMITH

step&compare

Technique
First seen 7/12/2026
Last seen 7/12/2026
Evidence 2 chunks

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The paper describes step&compare as a key verification technique applied to the core.
Core-V-Verif ← uses 100% 1e
step&compare was used in Core-V-Verif to keep DUT and ISS synchronized.
Reference Model uses → 100% 1e
step&compare synchronizes the DUT with the reference model/ISS.
Instruction Set Simulator uses → 100% 1e
step&compare steps the ISS only after the DUT retires an instruction.