Instruction Set Simulator
ConceptAn instruction set simulator (ISS) appears in the cited evidence as a software model used to execute or check instruction-level behavior. Spike is used as a RISC-V ISS in UVM and lockstep co-simulation verification flows, while QEMU is presented as a basis for generated ISS frontends from OpenVADL processor descriptions.
First seen 5/25/2026
Last seen 6/9/2026
Evidence 50 chunks
Wiki v5
WIKI
Instruction Set Simulator
An instruction set simulator (ISS) is used in the cited evidence as a model for instruction-level processor behavior. In the RISC-V verification evidence, Spike is identified as a RISC-V instruction set simulator used to validate correct instruction execution. In the OpenVADL evidence, QEMU is used as the basis for generating a QEMU-based ISS frontend from a processor description. [spike-as-iss] [qemu-based-iss]
Role in RISC-V verification
NEIGHBORHOOD
8 nodes · 11 edgesgraph · Instruction Set Simulator · depth=1
RELATIONSHIPS
22 connectionsAn ISS contains an instruction decoder unit.
Handling of illegal instructions is an important aspect of ISS correctness.
STTVC generates test vectors to evaluate and validate Instruction Set Simulators.
Spike is an instruction set simulator implementing the RISC-V ISA.
The generated C++ ISS is an implementation of an instruction set simulator.
Abstract ISS are based on the instruction set architecture rather than gate-level implementation.
An ISS models Control and Status Registers as part of the processor state.
The paper proposes and evaluates a method to verify instruction set simulators.
A virtual prototype contains an instruction set simulator as its central component
An ISS operates using the fetch-decode-execute cycle
Virtual prototyping relies on ISS for software simulation
STMicroelectronics uses ISS models for hardware verification.
QEMU is an open source machine emulator that implements an instruction set simulator.
ISS performance and applicability is contrasted with gate-level simulation.
Forvis is an instruction set simulator for RISC-V.
The RISC-V Virtual Prototype contains an ISS for RV32IMA.
An ISS contains a register file with registers including CSRs.
The ISS includes Control and Status Registers.
Simulation-based verification uses ISSs as executable specifications.
ISS are based on the ISA for their simulation model.
ISS is used for pre-silicon software development.
The paper focuses on testing and validating Instruction Set Simulators.
CITATIONS
9 sources9 citations — click to expand
[6] qemu-based-iss Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[7] qemu-tcg Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[8] qemu-generation Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
[9] openvadl-conclusion Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL