Instruction Set Simulator

CodeArtifact

Instruction Set Simulator (ISS) is a verification-support code artifact developed alongside a RISC-V random instruction generator for whole-processor verification of a two-way superscalar out-of-order RISC-V processor.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

The Instruction Set Simulator (ISS) is referenced as a code artifact developed for whole-processor verification of a RISC-V processor. In the cited verification work, individual processor units were verified first, including Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer. The verification effort then moved to the whole processor, for which both a RISC-V random instruction generator (RIG) and an Instruction Set Simulator (ISS) were developed.

Verification context

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RISC-V uses → 90% 1e

The Instruction Set Simulator is developed for RISC-V to verify processor behavior.

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CITATIONS

4 sources

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[1] The Instruction Set Simulator was developed for whole-processor verification after unit-level verification of Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer. [PDF] UVM-based verification of RISC-V superscalar processors

[2] The ISS was developed together with a RISC-V random instruction generator. [PDF] UVM-based verification of RISC-V superscalar processors

[3] The processor under verification is a two-way superscalar out-of-order microprocessor implementing the RISC-V ISA. [PDF] UVM-based verification of RISC-V superscalar processors

[4] The RISC-V random instruction generator was intended to produce instruction sequences that exercise architectural features, including rare corner cases. [PDF] UVM-based verification of RISC-V superscalar processors