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Instruction Set Simulator

CodeArtifact WIKI v1 · 5/28/2026

Instruction Set Simulator (ISS) is a verification-support code artifact developed alongside a RISC-V random instruction generator for whole-processor verification of a two-way superscalar out-of-order RISC-V processor.

Overview

The Instruction Set Simulator (ISS) is referenced as a code artifact developed for whole-processor verification of a RISC-V processor. In the cited verification work, individual processor units were verified first, including Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer. The verification effort then moved to the whole processor, for which both a RISC-V random instruction generator (RIG) and an Instruction Set Simulator (ISS) were developed.

Verification context

The processor under verification is described as a two-way superscalar out-of-order microprocessor implementing the RISC-V Instruction Set Architecture (ISA). Its pipeline includes a front end for instruction fetch and decode, register renaming, issue logic, execution and write-back stages, and a Re-Order Buffer used to preserve correct program order during retirement.

Within this context, the ISS belongs to the whole-processor verification flow rather than to the earlier unit-level verification steps. The evidence states that the ISS was developed together with the RISC-V random instruction generator when verification progressed from individual units to the full processor.

Relationship to the random instruction generator

The ISS was developed alongside a RISC-V random instruction generator. The generator's stated goal was to provide instruction sequences that effectively exercise architectural features of the processor, including rarely encountered corner cases. The provided evidence does not describe the ISS interface, implementation language, supported instruction subset, execution model, or exact checking mechanism.

Evidence-backed scope

Supported by the available evidence:

  • The artifact is an Instruction Set Simulator (ISS).
  • It was developed for use in whole-processor verification.
  • It was developed together with a RISC-V random instruction generator.
  • The verification target was a two-way superscalar out-of-order RISC-V processor.

Not established by the provided evidence:

  • Whether the ISS is cycle-accurate or functional-only.
  • Which RISC-V extensions or privilege levels it supports.
  • How it communicates with the design-under-verification testbench.
  • Whether it produces architectural traces, register/memory signatures, or pass/fail comparisons.

LINKED ENTITIES

1 links
RISC-V USES

CITATIONS

4 sources
4 citations
[1] The Instruction Set Simulator was developed for whole-processor verification after unit-level verification of Instruction Fetch, Register Renaming, Issue, and ReOrder Buffer. [PDF] UVM-based verification of RISC-V superscalar processors
[2] The ISS was developed together with a RISC-V random instruction generator. [PDF] UVM-based verification of RISC-V superscalar processors
[3] The processor under verification is a two-way superscalar out-of-order microprocessor implementing the RISC-V ISA. [PDF] UVM-based verification of RISC-V superscalar processors
[4] The RISC-V random instruction generator was intended to produce instruction sequences that exercise architectural features, including rare corner cases. [PDF] UVM-based verification of RISC-V superscalar processors