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cv32e40p

CodeArtifact
First seen 6/8/2026
Last seen 8/7/2026
Evidence 10 chunks

NEIGHBORHOOD

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RELATIONSHIPS

8 connections
RISC-V implements → 100% 3e
cv32e40p is a RISC-V CPU implementation.
ElectraIC Advanced Verification Suite (EAVS) ← evaluates 2e
EAVS is used to evaluate and verify the cv32e40p RISC-V core.
Advanced Verification Suite for RISC-V Cores ← evaluates 2e
The paper evaluates the cv32e40p RISC-V core as a case study.
System-on-Chip (SoC) part of → 100% 2e
cv32e40p is used as the CPU within a minimalistic SoC.
Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks ← uses 100% 1e
The paper uses the cv32e40p RISC-V CPU as the device under test.
RISC-V ISA implements → 1e
cv32e40p is a RISC-V core that implements the RISC-V ISA.
RISC-V Formal Interface (RVFI) uses → 1e
cv32e40p exposes RISC-V Formal Interface signals used by the RVFI Agent.
openhwgroup authored by → 100% 1e
The cv32e40p is maintained by the OpenHW Group.