Advanced Verification Suite for RISC-V Cores
PaperFirst seen 6/8/2026
Last seen 6/8/2026
Evidence 2 chunks
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11 connectionsThe paper evaluates the cv32e40p RISC-V core as a case study.
The paper is authored by Merve Eyüboğlu.
The paper is authored by Ibrahim Mouamar Ali Ahmed.
The paper is authored by Melike Atay Karabalkan.
The paper is authored by Berna Ors.
The paper is affiliated with ElectraIC.
The paper is affiliated with Istanbul Technical University.
The paper introduces the ElectraIC Advanced Verification Suite (EAVS).
The paper mentions and compares Force-riscv as a related instruction generator.
The paper is authored by Murat Tökez.
The paper mentions and compares Google riscv-dv as a related instruction generator.