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Google RISCV-DV

Tool

Google RISCV-DV (riscv-dv) is an instruction set generator (ISG) for the RISC-V instruction set architecture that produces randomly generated assembly instructions according to configurable test scenarios. It serves as a foundational tool in RISC-V processor verification, with COREV-DV and other derivative tools built on top of it.

First seen 6/8/2026
Last seen 9/24/2026
Evidence 2 chunks
Wiki v1

WIKI

Overview

Google RISCV-DV (also written as riscv-dv) is an instruction set generator (ISG) for the RISC-V instruction set architecture. As an ISG, it produces assembly files containing configured instructions according to targeted test scenarios, where the instructions are randomly generated in accordance with the scenario's constraints.

Role in RISC-V Processor Verification

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections
Instruction Set Generator (ISG) implements → 1e
Google riscv-dv implements an instruction set generator for RISC-V.
Advanced Verification Suite for RISC-V Cores ← compares with 1e
The paper mentions and compares Google riscv-dv as a related instruction generator.

LINKED ENTITIES

3 links
COREV-DV extended_by COREV-DV is explicitly described as being layered on top of Google riscv-dv in the EAVS paper.
spike related_to Spike is used as the ISS golden reference model in EAVS, the same verification environment that uses COREV-DV (layered on Google riscv-dv) as its instruction generator.
force-riscv related_to Force-riscv is another RISC-V instruction set generator mentioned alongside Google riscv-dv in the same evidence.

CITATIONS

9 sources
9 citations — click to expand
[1] Google RISCV-DV is an instruction set generator (ISG) for the RISC-V ISA Advanced Verification Suite for RISC-V Cores
[2] ISG produces assembly files with configured instructions randomly generated per scenario constraints Advanced Verification Suite for RISC-V Cores
[3] COREV-DV is layered on top of Google riscv-dv Advanced Verification Suite for RISC-V Cores
[4] EAVS-DV is proposed as an enhancement to COREV-DV Advanced Verification Suite for RISC-V Cores
[5] Force-riscv is an ISG from OpenHW Group supporting all instructions of RV32GC Advanced Verification Suite for RISC-V Cores
[6] Generated assembly files are compiled to machine language, written to memory, and delivered to the core Advanced Verification Suite for RISC-V Cores
[7] EAVS includes ISS, YAML configuration files, and a RISC-V Core UVM Testbench Advanced Verification Suite for RISC-V Cores
[8] Spike is a RISC-V ISA simulator officially released by RISC-V International Foundation, used as golden reference model in EAVS Advanced Verification Suite for RISC-V Cores
[9] EAVS demonstrated with verification of cv32e40p core as example Advanced Verification Suite for RISC-V Cores