Skip to content
STIMSMITH

Google RISCV-DV

Tool WIKI v1 · 9/24/2026

Google RISCV-DV (riscv-dv) is an instruction set generator (ISG) for the RISC-V instruction set architecture that produces randomly generated assembly instructions according to configurable test scenarios. It serves as a foundational tool in RISC-V processor verification, with COREV-DV and other derivative tools built on top of it.

Overview

Google RISCV-DV (also written as riscv-dv) is an instruction set generator (ISG) for the RISC-V instruction set architecture. As an ISG, it produces assembly files containing configured instructions according to targeted test scenarios, where the instructions are randomly generated in accordance with the scenario's constraints.

Role in RISC-V Processor Verification

In RISC-V processor verification flows, instruction set generators create test programs that exercise processor implementations. The assembly files generated by the instruction generator are compiled using a compiler into machine language, written into memory defined within a memory agent, and subsequently delivered to the design under test (DUT) for verification against a reference model.

Google RISCV-DV is mentioned alongside other RISC-V instruction generators, including Force-riscv, an ISG from OpenHW Group that supports all instructions of RV32GC.

Derivative and Related Tools

COREV-DV

COREV-DV is layered on top of Google RISCV-DV, extending its instruction generation capabilities for RISC-V core verification.

EAVS-DV

The ElectraIC Advanced Verification Suite (EAVS) uses COREV-DV as its instruction generator and proposes EAVS-DV as an enhancement to COREV-DV, further building on the Google RISCV-DV foundation.

Use in the ElectraIC Advanced Verification Suite (EAVS)

Google RISCV-DV has been used (via COREV-DV) in the ElectraIC Advanced Verification Suite (EAVS), a verification environment designed for any RISC-V core. EAVS includes an Instruction Set Simulator (ISS), YAML configuration files, and a RISC-V Core Universal Verification Methodology (UVM) Testbench containing a RISC-V core as the DUT, along with an instruction generator, compiler, and base test. The ISS uses Spike, a RISC-V ISA simulator officially released by the RISC-V International Foundation, operating as the golden reference model to determine whether the core's executed instructions are correct. EAVS has been demonstrated with the verification of the cv32e40p core as an example.

LINKED ENTITIES

3 links
COREV-DV extended_by
spike related_to
force-riscv related_to

CITATIONS

9 sources
9 citations
[1] Google RISCV-DV is an instruction set generator (ISG) for the RISC-V ISA Advanced Verification Suite for RISC-V Cores
[2] ISG produces assembly files with configured instructions randomly generated per scenario constraints Advanced Verification Suite for RISC-V Cores
[3] COREV-DV is layered on top of Google riscv-dv Advanced Verification Suite for RISC-V Cores
[4] EAVS-DV is proposed as an enhancement to COREV-DV Advanced Verification Suite for RISC-V Cores
[5] Force-riscv is an ISG from OpenHW Group supporting all instructions of RV32GC Advanced Verification Suite for RISC-V Cores
[6] Generated assembly files are compiled to machine language, written to memory, and delivered to the core Advanced Verification Suite for RISC-V Cores
[7] EAVS includes ISS, YAML configuration files, and a RISC-V Core UVM Testbench Advanced Verification Suite for RISC-V Cores
[8] Spike is a RISC-V ISA simulator officially released by RISC-V International Foundation, used as golden reference model in EAVS Advanced Verification Suite for RISC-V Cores
[9] EAVS demonstrated with verification of cv32e40p core as example Advanced Verification Suite for RISC-V Cores