COREV-DV

Tool

COREV-DV is a library of SystemVerilog extensions to Google's riscv-dv instruction stream generator, used within the core-v-verif verification environment to generate directed, randomized test programs for CORE-V cores. It enables core-specific customization without modifying the upstream riscv-dv project, allowing core-v-verif to absorb Google updates seamlessly.

First seen 6/18/2026

Last seen 7/12/2026

Evidence 2 chunks

Wiki v1

WIKI

COREV-DV

Overview

COREV-DV is the name given to a library of extensions to the Google riscv-dv instruction stream generator. It is used inside the core-v-verif verification project to produce randomized and directed instruction streams that exercise CORE-V cores such as CV32E40P.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

5 connections

riscv-dv extends → 100% 1e

COREV-DV is a library of extensions to the riscv-dv instruction stream generator.

Core-V-Verif ← uses 100% 1e

core-v-verif includes and uses COREV-DV extensions.

Core-V-Verif part of → 95% 1e

COREV-DV is a component library within the core-v-verif verification environment.

corev_asm_program_gen.sv ← part of 95% 1e

corev_asm_program_gen.sv is a file within the COREV-DV library.

CV32E40P ← uses 90% 1e

CV32E40P has core-specific extensions to COREV-DV as an example case.

LINKED ENTITIES

4 links

riscv-dv EXTENDS Extracted graph relationship

Core-V-Verif USES Extracted graph relationship

corev_asm_program_gen.sv PART_OF Extracted graph relationship

CV32E40P USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] COREV-DV is a library of extensions to the Google riscv-dv instruction stream generator. COREV-DV — CORE-V Verification Strategy documentation

[2] riscv-dv is implemented as a collection of SystemVerilog classes extending from uvm_object, and extending riscv-dv classes to modify behavior is straightforward. COREV-DV — CORE-V Verification Strategy documentation

[3] riscv-dv itself is not modified, allowing core-v-verif to easily take advantage of updates to the Google project. COREV-DV — CORE-V Verification Strategy documentation

[4] core-v-verif uses riscv-dv 'as is' and each core verified in core-v-verif is free to use whatever version of riscv-dv suits its needs. COREV-DV — CORE-V Verification Strategy documentation

[5] The non-core-specific version of COREV-DV resides at $CORE_V_VERIF/lib/corev-dv. COREV-DV — CORE-V Verification Strategy documentation

[6] When a Make target requires it, a specific hash of riscv-dv is cloned to $CORE_V_VERIF/$COREV_CORE/vendor_lib/riscv-dv, and the compile Makefiles compile in the required extensions. COREV-DV — CORE-V Verification Strategy documentation

[7] Core-specific COREV-DV extensions should be placed in $CORE_V_VERIF/$COREV_CORE/env/corev-dv. COREV-DV — CORE-V Verification Strategy documentation

[8] corev_asm_program_gen.sv at $CORE_V_VERIF/lib/corev-dv overrides riscv_gen_program_header::gen_program_header() to enforce the use of common symbols required by the board support package. COREV-DV — CORE-V Verification Strategy documentation

[9] Instructions for building and running a COREV-DV-generated test program are provided in the README at $CORE_V_VERIF/mk/uvmt. COREV-DV — CORE-V Verification Strategy documentation