CORE-V DV

Tool

CORE-V DV is an OpenHW/core-v-verif library of extensions to Google's RISCV-DV SystemVerilog/UVM RISC-V instruction stream generator. It lets CORE-V verification environments add common and core-specific instruction-generation behavior without modifying upstream RISCV-DV, and can be compiled into core-specific flows such as RV32IMC-oriented generation runs using the `corev_instr_base_test` UVM test.

First seen 6/18/2026

Last seen 9/24/2026

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CORE-V DV

Overview

CORE-V DV is a library of extensions to Google's RISCV-DV RISC-V instruction stream generator. The OpenHW documentation describes it as the name for extensions to the Google riscv-dv instruction stream generator, and a RISC-V Europe 2023 abstract describes COREV-DV as an OpenHW extension to RISCV-DV used to generate random instruction streams, including Xpulp instructions. [C1]

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

riscv-dv extends → 100% 1e

COREV-DV is a library of extensions to the riscv-dv instruction stream generator.

Core-V-Verif ← uses 100% 1e

core-v-verif includes and uses COREV-DV extensions.

Core-V-Verif part of → 95% 1e

COREV-DV is a component library within the core-v-verif verification environment.

corev_asm_program_gen.sv ← part of 95% 1e

corev_asm_program_gen.sv is a file within the COREV-DV library.

CV32E40P ← uses 90% 1e

CV32E40P has core-specific extensions to COREV-DV as an example case.

riscv-dv uses → 86% 1e

The corev-dv flow invokes riscv-dv compile and generation steps to produce tests.

UVM uses → 70% 1e

The generation command passes a UVM test name, indicating the use of UVM within the CORE-V DV flow.

corev_instr_base_test uses → 78% 1e

The flow specifies corev_instr_base_test as the active UVM test name in its run flags.

RV32IMC targets ISA → 64% 1e

Within the corev-dv flow, RISCV-DV is compiled with the rv32imc target, indicating the ISA focus.

LINKED ENTITIES

4 links

riscv-dv USES Extracted graph relationship

UVM USES Extracted graph relationship

corev_instr_base_test USES Extracted graph relationship

RV32IMC TARGETS_ISA Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] CORE-V DV is a library/OpenHW extension to Google's RISCV-DV instruction stream generator and is used for random instruction streams including Xpulp instructions. COREV-DV — CORE-V Verification Strategy documentation

[2] RISCV-DV is implemented as SystemVerilog classes extending `uvm_object`; CORE-V DV extends RISCV-DV classes and does not modify RISCV-DV so that core-v-verif can take advantage of Google project updates. COREV-DV — CORE-V Verification Strategy documentation

[3] core-v-verif mostly uses RISCV-DV as-is, and each verified core may use the RISCV-DV version that suits its needs. COREV-DV — CORE-V Verification Strategy documentation

[4] The common, non-core-specific CORE-V DV library is located at `$CORE_V_VERIF/lib/corev-dv` and contains extensions intended to be common across most CORE-V cores. COREV-DV — CORE-V Verification Strategy documentation

[5] When required by a Make target, a specific RISCV-DV hash is cloned under `$CORE_V_VERIF/$COREV_CORE/vendor_lib/riscv-dv`, and compile Makefiles include the extensions needed for a core-specific CORE-V DV test. COREV-DV — CORE-V Verification Strategy documentation

[6] An xrun Make flow compiles RISCV-DV/CORE-V DV using RISCV-DV `target/rv32imc`, `user_extension`, and `tests` include directories plus the CORE-V DV manifest, and generates with `+UVM_TESTNAME=corev_instr_base_test` and other example generator options. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab

[7] Core-specific CORE-V DV extensions should be placed in `$CORE_V_VERIF/$COREV_CORE/env/corev-dv`; `corev_asm_program_gen.sv` overrides `riscv_gen_program_header::gen_program_header()` to enforce common BSP symbols and may need core-specific extensions. COREV-DV — CORE-V Verification Strategy documentation

[8] CORE-V verification stimulus includes pseudo-random programs generated by RISCV-DV/COREV-DV, manually generated C and assembly programs, OBI bus-delay randomization, and UVM agents for interrupts and debug requests. customizing an open-source RISC-V core at industrial-grade