COREV-DV

Overview

COREV-DV is the name given to a library of extensions to the Google riscv-dv instruction stream generator. It is used inside the core-v-verif verification project to produce randomized and directed instruction streams that exercise CORE-V cores such as CV32E40P.

Architecture and Design Rationale

riscv-dv is implemented as a collection of SystemVerilog classes that extend from uvm_object, so extending riscv-dv classes to modify their behavior is straightforward. For cases where a specific instruction stream is required, COREV-DV implements it as an extension of an existing riscv-dv class. The key design choice is that riscv-dv itself is not modified, which allows core-v-verif to easily take advantage of upstream updates from the Google project.

For the most part, core-v-verif uses riscv-dv "as is," and each core that is verified in core-v-verif is free to use whatever version of riscv-dv suits the core's needs.

Repository Layout

A non-core-specific version of COREV-DV resides at:

$CORE_V_VERIF/lib/corev-dv

This location contains a set of extensions to riscv-dv that are intended to be common across all (or at least most) CORE-V cores.

Using COREV-DV

When a Make target requires it, a specific hash of riscv-dv is cloned to:

$CORE_V_VERIF/$COREV_CORE/vendor_lib/riscv-dv

The compile Makefiles compile in the required extensions to generate the core-specific version of COREV-DV needed for a test. Instructions for building and running a COREV-DV-generated test program are provided in the README at $CORE_V_VERIF/mk/uvmt under the corev-dv generated tests section.

Extending COREV-DV

It is expected that each unique core will require multiple extensions to riscv-dv. These core-specific extensions should be placed in:

$CORE_V_VERIF/$COREV_CORE/env/corev-dv

A representative example of a base extension is corev_asm_program_gen.sv, located in $CORE_V_VERIF/lib/corev-dv/. This file implements an override of riscv_gen_program_header::gen_program_header() to enforce the use of common symbols required by the board support package (BSP). Because each core's verification environment is likely to use a core-specific BSP, each core is expected to implement its own core-specific extensions to corev_asm_program_gen.sv.

Example Directory Tree

A simplified view of the core-v-verif directory tree illustrates where riscv-dv is located, where the base COREV-DV extensions reside, and where core-specific extensions (for example for CV32E40P) are added:

$CORE_V_VERIF/
├── lib/
│   └── corev-dv/                  # non-core-specific COREV-DV extensions
│       └── corev_asm_program_gen.sv
└── <COREV_CORE>/
    ├── env/
    │   └── corev-dv/              # core-specific COREV-DV extensions
    └── vendor_lib/
        └── riscv-dv/              # cloned Google riscv-dv at pinned hash

Integration with core-v-verif

COREV-DV is part of the broader core-v-verif verification strategy. It is consumed by core-v-verif to generate instruction streams that drive UVM-based testbenches against RTL implementations of CORE-V cores, enabling constrained-random and directed verification flows that are consistent across the CORE-V ecosystem.