CORE-V DV

Overview

CORE-V DV is a library of extensions to Google's RISCV-DV RISC-V instruction stream generator. The OpenHW documentation describes it as the name for extensions to the Google riscv-dv instruction stream generator, and a RISC-V Europe 2023 abstract describes COREV-DV as an OpenHW extension to RISCV-DV used to generate random instruction streams, including Xpulp instructions. [C1]

RISCV-DV is implemented using SystemVerilog classes that extend uvm_object, so CORE-V DV customizations are implemented by extending RISCV-DV classes rather than modifying RISCV-DV itself. This design lets core-v-verif consume updates from the Google project while keeping CORE-V-specific behavior in extension code. [C2]

Role in core-v-verif

In the core-v-verif flow, RISCV-DV is used mostly "as is". Each core verified in core-v-verif may use the RISCV-DV version that suits that core's needs, while CORE-V DV provides reusable and core-specific extensions around it. [C3]

A non-core-specific CORE-V DV library resides at:

$CORE_V_VERIF/lib/corev-dv

This directory contains extensions intended to be common across all, or at least most, CORE-V cores. [C4]

Build and generation flow

When a Make target requires RISCV-DV, a specific RISCV-DV hash is cloned to:

$CORE_V_VERIF/$COREV_CORE/vendor_lib/riscv-dv

The compile Makefiles then compile the required extensions to produce the core-specific CORE-V DV variant needed for a test. The OpenHW documentation points users to the README under $CORE_V_VERIF/mk/uvmt, in the corev-dv generated tests section, for build and run instructions. [C5]

A concrete xrun-based flow in the provided evidence adds Make rules to compile and generate with the Google instruction stream generator. The compile rule includes RISCV-DV target, user-extension, and test directories, plus the CORE-V DV package and manifest:

+incdir+$(RISCVDV_PKG)/target/rv32imc
+incdir+$(RISCVDV_PKG)/user_extension
+incdir+$(RISCVDV_PKG)/tests
+incdir+$(COREVDV_PKG)
-f $(COREVDV_PKG)/manifest.f

The corresponding generation rule runs with +UVM_TESTNAME=corev_instr_base_test, emits assembly under $(CORE_TEST_DIR)/google-riscv-dv, and shows example generator options such as +instr_cnt=10000, +directed_instr_0=riscv_int_numeric_corner_stream,4, +boot_mode=m, and disabling fence, data page, branch/jump, and CSR instruction generation for that run. [C6]

Extension model

CORE-V DV expects individual cores to need multiple RISCV-DV extensions. Core-specific extensions should be placed in:

$CORE_V_VERIF/$COREV_CORE/env/corev-dv

A documented example is:

$CORE_V_VERIF/lib/corev-dv/corev_asm_program_gen.sv

This file overrides riscv_gen_program_header::gen_program_header() to enforce common symbols required by the board support package. Because each core verification environment is likely to use a core-specific BSP, the documentation expects cores to implement core-specific extensions to corev_asm_program_gen.sv. [C7]

Verification-stimulus context

CORE-V DV is one source of processor stimulus in the broader CORE-V verification environment. The RISC-V Europe abstract lists automatic pseudo-random test-program generation via RISCV-DV and the OpenHW COREV-DV extension alongside manually generated C and assembly programs, OBI bus-delay randomization, and UVM agents that randomize interrupts and debug requests. [C8]

Simplified repository layout

$CORE_V_VERIF/
├── lib/
│   └── corev-dv/                  # common CORE-V DV extensions
│       └── corev_asm_program_gen.sv
└── $COREV_CORE/
    ├── env/
    │   └── corev-dv/              # core-specific CORE-V DV extensions
    └── vendor_lib/
        └── riscv-dv/              # RISCV-DV clone used by the core flow

This layout reflects the documented separation between common CORE-V DV extensions, per-core extensions, and the core-local RISCV-DV clone. [C4] [C5] [C7]