RV32IMC

ISA

RV32IMC is a 32-bit RISC-V base instruction set architecture (ISA) profile combining the RV32I base integer ISA with the M integer multiply/divide and C compressed instruction extensions. It is widely targeted by open-source verification tools such as Google RISCV-DV and the OpenHW Group CORE-V DV environment, and it is used as the embedded control core in heterogeneous FPGA-based acceleration research prototypes.

First seen 9/24/2026

Last seen 9/24/2026

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Overview

RV32IMC is a 32-bit configuration of the open RISC-V instruction set architecture (ISA). It combines:

RV32I — the base 32-bit integer instruction set.
M — hardware support for integer multiplication and division.
C — the compressed instruction extension, which reduces code size by encoding common operations in 16-bit instructions.

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv-dv ← targets ISA 82% 1e

The compile command includes the RISCV-DV target directory for rv32imc.

COREV-DV ← targets ISA 64% 1e

Within the corev-dv flow, RISCV-DV is compiled with the rv32imc target, indicating the ISA focus.

LINKED ENTITIES

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riscv-dv TARGETS_ISA Extracted graph relationship

COREV-DV TARGETS_ISA Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] RV32IMC combines the RV32I base integer ISA with the M integer multiply/divide and C compressed instruction extensions. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab

[2] RISCV-DV ships a target/rv32imc include directory used when compiling RV32IMC instruction-stream generators integrated with the CORE-V DV environment. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab

[3] SynapticCore-X integrates a lightweight RV32IMC RISC-V control core with a configurable neural compute tile and achieves timing closure at 100 MHz on the Zynq-7020 while consuming 6.1% LUTs, 32.5% DSPs, and 21.4% BRAMs, validated on PYNQ-Z2. SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration

[4] SPARX is built around a heterogeneous RV32IMC RISC-V SoC combining a custom instruction extension, an approximate logarithmic CNN acceleration unit, a privacy engine, and challenge-response authentication, targeting 250 MHz on Xilinx VC707 with 58.4 GOPS/W energy efficiency. SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC