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RV32IMC

ISA WIKI v1 · 9/24/2026

RV32IMC is a 32-bit RISC-V base instruction set architecture (ISA) profile combining the RV32I base integer ISA with the M integer multiply/divide and C compressed instruction extensions. It is widely targeted by open-source verification tools such as Google RISCV-DV and the OpenHW Group CORE-V DV environment, and it is used as the embedded control core in heterogeneous FPGA-based acceleration research prototypes.

Overview

RV32IMC is a 32-bit configuration of the open RISC-V instruction set architecture (ISA). It combines:

  • RV32I — the base 32-bit integer instruction set.
  • M — hardware support for integer multiplication and division.
  • C — the compressed instruction extension, which reduces code size by encoding common operations in 16-bit instructions.

The combined RV32IMC profile provides a compact, efficient instruction set suited to embedded control cores and constrained hardware targets.

Role in Verification Tooling

RV32IMC is the targeted ISA in the example xrun-based build flow used to integrate Google's RISCV-DV instruction stream generator and the CORE-V DV environment. In the recorded Makefile rules for a CVA6/zicfiss-based project, the compilation step explicitly references the RV32IMC target directory:

+incdir+$(RISCVDV_PKG)/target/rv32imc \
+incdir+$(RISCVDV_PKG)/user_extension \
+incdir+$(RISCVDV_PKG)/tests \
+incdir+$(COREVDV_PKG) \
-f $(COREVDV_PKG)/manifest.f

This shows that RISCV-DV ships a dedicated rv32imc target include directory used when compiling random instruction-stream generators, and that CORE-V DV consumes that generator output for verification of RV32IMC-compliant cores (evidence chunk 341c50c2-db06-420e-ad4d-3b7d4070a391).

Use as an Embedded Control Core

RV32IMC is repeatedly chosen as the lightweight host/control ISA for heterogeneous acceleration research prototypes on FPGA platforms:

  • SynapticCore-X (arxiv 2511.12616v1) integrates a lightweight RV32IMC RISC-V control core alongside a configurable neural compute tile. The full design is delivered as open-source SystemVerilog with a reproducible Vivado build pipeline achieving timing closure at 100 MHz on the Zynq-7020, consuming 6.1% LUTs, 32.5% DSPs, and 21.4% BRAMs, and is validated on the PYNQ-Z2 board.
  • SPARX (arxiv 2606.09946v2) presents a heterogeneous RV32IMC RISC-V System-on-Chip (SoC) that combines a custom RISC-V instruction extension, an approximate logarithmic CNN acceleration unit, a differential-noise-based privacy engine, and challenge-response authentication. It targets 250 MHz on a Xilinx VC707 and reports 58.4 GOPS/W energy efficiency.

These instances illustrate RV32IMC's typical deployment as the embedded controller in mixed control-plus-acceleration FPGA SoCs.

See Also

  • RISCV-DV — instruction stream generator that ships an RV32IMC target include directory.
  • CORE-V DV — verification environment built on top of RISCV-DV, also targeting RV32IMC.

LINKED ENTITIES

2 links
riscv-dv TARGETS_ISA
COREV-DV TARGETS_ISA

CITATIONS

4 sources
4 citations
[1] RV32IMC combines the RV32I base integer ISA with the M integer multiply/divide and C compressed instruction extensions. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab
[2] RISCV-DV ships a target/rv32imc include directory used when compiling RV32IMC instruction-stream generators integrated with the CORE-V DV environment. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab
[3] SynapticCore-X integrates a lightweight RV32IMC RISC-V control core with a configurable neural compute tile and achieves timing closure at 100 MHz on the Zynq-7020 while consuming 6.1% LUTs, 32.5% DSPs, and 21.4% BRAMs, validated on PYNQ-Z2. SynapticCore-X: A Modular Neural Processing Architecture for Low-Cost FPGA Acceleration
[4] SPARX is built around a heterogeneous RV32IMC RISC-V SoC combining a custom instruction extension, an approximate logarithmic CNN acceleration unit, a privacy engine, and challenge-response authentication, targeting 250 MHz on Xilinx VC707 with 58.4 GOPS/W energy efficiency. SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC