force-riscv

Tool

force-riscv is an OpenHW Group GitHub repository described as an “Instruction Set Generator initially contributed by Futurewei.” The repository is public and is not marked as a fork in the provided GitHub metadata.

First seen 5/25/2026

Last seen 9/5/2026

Evidence 15 chunks

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WIKI

force-riscv

Overview

force-riscv is a tool repository hosted on GitHub under openhwgroup/force-riscv. GitHub metadata describes the project as an “Instruction Set Generator initially contributed by Futurewei.”

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NEIGHBORHOOD

3 nodes · 2 edges

graph · force-riscv · depth=1

RELATIONSHIPS

22 connections

DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification ← uses 100% 2e

The paper uses FORCE-RISCV as the random instruction stream generator for producing test sequences.

Single instruction isolation for RISC-V vector test failures ← mentions 95% 2e

The paper mentions FORCE-RISCV as a related ISG tool.

Instruction Stream Generator implements → 100% 2e

FORCE-RISCV is an implementation of an instruction stream generator for RISC-V designs.

DeepVerifier ← uses 100% 2e

DeepVerifier uses FORCE-RISCV as the instruction stream generator to produce initial test sequences.

Futurewei ← introduces 97% 2e

force-riscv was initially contributed by Futurewei, indicating Futurewei introduced the tool.

Open-Source RISC-V Vector Test Suites: A Comparative Analysis ← evaluates 100% 2e

The paper evaluates FORCE-RISCV as one of seven open-source test suites.

Advanced Verification Suite for RISC-V Cores ← compares with 1e

The paper mentions and compares Force-riscv as a related instruction generator.

openhwgroup ← uses 100% 1e

FORCE-RISCV is maintained by the OpenHW Group.

Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs ← mentions 90% 1e

The paper mentions FORCE-RISCV as an alternative instruction generation tool.

chipsalliance published by → 70% 1e

FORCE-RISCV is published by the OpenHW Group, which is part of CHIPS Alliance.

instruction sequence generation uses → 100% 1e

FORCE-RISCV is an Instruction Sequence Generator designed to generate tests for processor design verification.

Signature-based Checking uses → 100% 1e

FORCE-RISCV uses signature-based checking.

riscv-ovpsim uses → 100% 1e

FORCE-RISCV uses riscvOVPsim as its coverage tool.

Handcar ISS uses → 100% 1e

FORCE-RISCV uses Handcar as its ISS.

Random Instruction Generation uses → 100% 1e

FORCE-RISCV utilizes randomization to select instructions, registers, addresses, and data.

Instruction Set Generator implements → 98% 1e

force-riscv is described as an Instruction Set Generator, meaning it implements that concept.

openhwgroup ← introduces 90% 1e

FORCE-RISCV is hosted under openhwgroup on GitHub.

RISC-V ISA targets ISA → 100% 1e

FORCE-RISCV is an instruction stream generator that adheres to the RISC-V ISA specifications.

Instruction Set Generator (ISG) implements → 1e

Force-riscv implements the Instruction Set Generator concept.

openhwgroup published by → 1e

Force-riscv is published by the OpenHW Group.

RISC-V ISA uses → 1e

Force-riscv targets the RISC-V ISA.

RV32GC uses → 1e

Force-riscv supports all instructions of the RV32GC ISA.

LINKED ENTITIES

2 links

openhwgroup repository_owner The GitHub metadata identifies the repository as openhwgroup/force-riscv and includes octolytics repository owner fields for openhwgroup.

Futurewei initial_contributor The repository description states that the Instruction Set Generator was initially contributed by Futurewei.

CITATIONS

4 sources

4 citations — click to collapse

[1] force-riscv is described as an “Instruction Set Generator initially contributed by Futurewei.” openhwgroup/force-riscv

[2] The repository is identified as openhwgroup/force-riscv. openhwgroup/force-riscv

[3] The repository has a Git import URL of https://github.com/openhwgroup/force-riscv.git. openhwgroup/force-riscv

[4] The GitHub metadata marks the repository as public and not a fork. openhwgroup/force-riscv