force-riscv
Toolforce-riscv is an OpenHW Group GitHub repository described as an “Instruction Set Generator initially contributed by Futurewei.” The repository is public and is not marked as a fork in the provided GitHub metadata.
First seen 5/25/2026
Last seen 6/8/2026
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WIKI
force-riscv
Overview
force-riscv is a tool repository hosted on GitHub under openhwgroup/force-riscv. GitHub metadata describes the project as an “Instruction Set Generator initially contributed by Futurewei.”
NEIGHBORHOOD
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7 connectionsforce-riscv was initially contributed by Futurewei, indicating Futurewei introduced the tool.
Force-riscv implements the Instruction Set Generator concept.
force-riscv is described as an Instruction Set Generator, meaning it implements that concept.
Force-riscv targets the RISC-V ISA.
Force-riscv supports all instructions of the RV32GC ISA.
The paper mentions and compares Force-riscv as a related instruction generator.
Force-riscv is published by the OpenHW Group.
LINKED ENTITIES
2 linksopenhwgroup repository_owner The GitHub metadata identifies the repository as openhwgroup/force-riscv and includes octolytics repository owner fields for openhwgroup.
Futurewei initial_contributor The repository description states that the Instruction Set Generator was initially contributed by Futurewei.
CITATIONS
4 sources4 citations — click to collapse
[1] force-riscv is described as an “Instruction Set Generator initially contributed by Futurewei.” openhwgroup/force-riscv
[3] The repository has a Git import URL of https://github.com/openhwgroup/force-riscv.git. openhwgroup/force-riscv