DeepVerifier

Tool

First seen 6/12/2026

Last seen 6/12/2026

Evidence 15 chunks

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27 connections

force-riscv uses → 100% 2e

DeepVerifier uses FORCE-RISCV as the instruction stream generator to produce initial test sequences.

Coverage-Guided Verification implements → 100% 2e

DeepVerifier implements coverage-guided verification by learning relationships between test sequences and coverage scores.

transformer language model for instruction sequences uses → 100% 2e

DeepVerifier uses a transformer language model to represent and generate RISC-V instruction sequences.

gradient-based sequence update uses → 100% 2e

DeepVerifier employs a gradient-based sequence update strategy to enhance test sequences toward higher coverage.

coverage score prediction uses → 100% 2e

DeepVerifier uses a coverage score predictor that accurately estimates coverage values for test sequences.

ISA syntax correction uses → 100% 2e

DeepVerifier applies ISA syntax correction to ensure optimized sequences remain compliant with RISC-V ISA.

RISC-V ISA targets ISA → 100% 2e

DeepVerifier targets the RISC-V ISA, customizing its language model and tokenizer for RISC-V assembly sequences.

cross-entropy loss for sequence generation uses → 100% 2e

DeepVerifier uses cross-entropy loss to train its transformer model for sequence generation.

sequential modeling task for test generation uses → 100% 2e

DeepVerifier uses a sequential modeling task to train its transformer to understand instruction sequence patterns.

Transformer architecture uses → 100% 2e

DeepVerifier uses the Transformer architecture as the backbone of its language model for instruction sequences.

multi-head self-attention uses → 100% 2e

DeepVerifier uses multi-head self-attention within its transformer blocks to capture instruction dependencies.

CPU processor design evaluates → 90% 2e

DeepVerifier evaluates CPU processor designs through coverage-guided test sequence generation.

test sequence tokenization uses → 100% 2e

DeepVerifier tokenizes RISC-V instruction sequences using a customized tokenizer.

instruction embedding uses → 100% 2e

DeepVerifier creates instruction embeddings as continuous vector representations for downstream coverage prediction.

Simulation-Based Verification uses → 90% 2e

DeepVerifier leverages simulation-based verification feedback to train its transformer model.

CPU processor design uses → 90% 1e

DeepVerifier targets CPU processor designs as the subject of functional verification.

mean square error loss for coverage prediction uses → 100% 1e

DeepVerifier uses MSE loss to train its coverage predictor.

GELU activation function uses → 100% 1e

DeepVerifier uses the GELU activation function in its transformer feed-forward network layers.

coverage metrics uses → 100% 1e

DeepVerifier is guided by coverage metrics to optimize test sequences.

Coverage Closure uses → 95% 1e

DeepVerifier aims to facilitate coverage closure by optimizing test sequences toward target coverage goals.

Synopsys VCS uses → 100% 1e

DeepVerifier uses Synopsys VCS as an RTL simulator to obtain coverage scores during training.

Verilator uses → 100% 1e

DeepVerifier uses Verilator as an RTL simulator to obtain coverage scores during training.

natural language processing uses → 90% 1e

DeepVerifier draws on NLP techniques to treat RISC-V assembly sequences as a domain-specific language.

positional encoding uses → 100% 1e

DeepVerifier uses positional encoding to incorporate sequence order information into instruction embeddings.

DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification ← introduces 100% 1e

The paper introduces the DeepVerifier framework for coverage-guided test sequence generation.

BART derived from → 95% 1e

DeepVerifier's transformer model is a customized version of BART adapted for RISC-V assembly sequence representation.

PalmTree derived from → 85% 1e

DeepVerifier draws inspiration from PalmTree, a prior assembly language representation model.