DeepVerifier
ToolFirst seen 6/12/2026
Last seen 9/15/2026
Evidence 33 chunks
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50 connectionsDeepVerifier uses FORCE-RISCV as the instruction sequence generator to produce training data.
DeepVerifier implements coverage-guided verification by using a language model to learn relationships between test sequences and coverage scores.
DeepVerifier's transformer model uses multi-head self-attention layers.
DeepVerifier uses Verilator as an RTL simulator to capture coverage scores.
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification ← introduces 100% 3e
The paper introduces DeepVerifier as a novel coverage-guided test generation framework.
DeepVerifier uses a transformer language model to learn semantic representations of test sequences.
DeepVerifier employs gradient-based optimization to update instruction sequences towards higher coverage.
DeepVerifier uses instruction sequence representation via tokenization and transformer embeddings.
DeepVerifier uses Synopsys VCS as an RTL simulator to capture coverage scores.
DeepVerifier is compared against an LSTM-based representation model as a baseline.
DeepVerifier uses coverage metrics to guide test sequence optimization.
DeepVerifier uses test sequence generation as its primary approach to coverage-guided verification.
DeepVerifier uses a transformer language model to represent and generate RISC-V instruction sequences.
DeepVerifier employs a gradient-based sequence update strategy to enhance test sequences toward higher coverage.
DeepVerifier uses a coverage score predictor that accurately estimates coverage values for test sequences.
DeepVerifier applies ISA syntax correction to ensure optimized sequences remain compliant with RISC-V ISA.
DeepVerifier targets the RISC-V ISA, customizing its language model and tokenizer for RISC-V assembly sequences.
DeepVerifier uses cross-entropy loss for the sequential modeling training task.
DeepVerifier uses MSE loss for coverage score prediction and gradient-based sequence optimization.
DeepVerifier uses token embeddings to map instruction tokens into continuous vectors.
DeepVerifier uses a custom RISC-V tokenizer to convert assembly instructions into token vectors.
DeepVerifier uses a RISC-V instruction syntax interpreter to ensure validity of updated instruction sequences.
DeepVerifier uses a coverage score predictor MLP as the prediction head for coverage estimation.
DeepVerifier targets functional verification of RISC-V processor designs.
DeepVerifier is evaluated on the BOOM out-of-order processor.
DeepVerifier is evaluated on the RocketChip processor.
DeepVerifier creates instruction embeddings as continuous vector representations for downstream coverage prediction.
DeepVerifier uses a sequential modeling task to train its transformer to understand instruction sequence patterns.
DeepVerifier tokenizes RISC-V instruction sequences using a customized tokenizer.
DeepVerifier leverages simulation-based verification feedback to train its transformer model.
DeepVerifier uses the Transformer architecture as the backbone of its language model for instruction sequences.
DeepVerifier evaluates CPU processor designs through coverage-guided test sequence generation.
DeepVerifier is compared against mutational fuzzing as a baseline.
DeepVerifier uses cross-entropy loss to train its transformer model for sequence generation.
DeepVerifier's architecture draws inspiration from PalmTree, a prior assembly language representation model.
DeepVerifier is fine-tuned from the BART-base model for RISC-V instruction sequence representation.
DeepVerifier uses a sequential modeling task for pre-training the transformer language model.
DeepVerifier's transformer model is a customized version of BART adapted for RISC-V assembly sequence representation.
DeepVerifier uses sinusoidal positional encoding to encode token position in sequences.
DeepVerifier uses MSE loss to train its coverage predictor.
DeepVerifier's feed-forward network uses GELU activation function.
DeepVerifier uses Hugging Face Transformers library for the BART-base model.
DeepVerifier draws on NLP techniques to treat RISC-V assembly sequences as a domain-specific language.
DeepVerifier aims to facilitate coverage closure by optimizing test sequences toward target coverage goals.
DeepVerifier targets CPU processor designs as the subject of functional verification.
DeepVerifier is compared against random instruction generation as a baseline.
DeepVerifier uses the GELU activation function in its transformer feed-forward network layers.
DeepVerifier uses positional encoding to incorporate sequence order information into instruction embeddings.
DeepVerifier is implemented using PyTorch.
DeepVerifier uses the AdamW optimizer for training the transformer and coverage predictor.