Synopsys VCS
ToolSynopsys VCS is documented in the provided evidence as an industry-standard commercial RTL simulator used to compile Verilog RTL into host executables for simulation, and as a verified simulator option for the RISCV-DV SystemVerilog/UVM instruction generator. Evidence also describes VCS constraint-solving/profiling behavior for constrained-random generator performance analysis.
First seen 5/24/2026
Last seen 7/18/2026
Evidence 29 chunks
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Synopsys VCS
Synopsys VCS is an RTL simulation tool used in hardware verification workflows. In the MorFuzz processor-fuzzing evaluation, the authors describe using Synopsys VCS as an "industry-standard commercial tool" to simulate hardware RTL designs. Their flow translates hardware modules to Verilog and compiles them into a host executable binary through the Synopsys VCS RTL simulator.
Use in RISC-V verification flows
NEIGHBORHOOD
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34 connectionsThe VCS Constraint Profiler is a feature within Synopsys VCS.
AMD uses Synopsys VCS as the constraint solver in their verification flow.
Synopsys VCS is a high-performance commercial RTL simulation tool
GoldenFuzz uses Synopsys VCS as an RTL simulation backend for DUT-level fuzzing.
Synopsys VCS is published by Synopsys as an industry-standard RTL simulator.
The hierarchical constrained-random approach uses the Synopsys VCS constraint solver for generation.
MorFuzz compiles hardware modules into a host executable binary through Synopsys VCS RTL simulator.
Synopsys VCS generates VDB files that are used in the coverage flow.
TheHuzz uses Synopsys VCS to simulate the target hardware and extract coverage metrics.
GenHuzz uses Synopsys VCS to generate hardware simulation traces and compute hardware coverage metrics.
ImperasDV integrates with Synopsys VCS for RTL simulation in the co-simulation flow.
Synopsys VCS implements the RACE solver as its default constraint solving mode.
RISCV-DV has been verified with Synopsys VCS.
VCS 2009.12 introduced a testcase extraction feature to extract the slowest partition from each randomize call.
The hierarchical constrained-random approach uses the Synopsys VCS constraint solver.
ProcessorFuzz uses Synopsys VCS to report industry-standard RTL coverage metrics.
DeepVerifier uses Synopsys VCS as an RTL simulator to obtain coverage scores during training.
The BDD solver is a constraint solver available within Synopsys VCS.
Synopsys VCS is used as the simulator in the verification methodology described in the paper.
The MCU testbench uses Synopsys VCS as its simulator.
Synopsys VCS is a product of Synopsys used in the verification flow.
Synopsys VCS is an industry-standard RTL simulator used to execute the design under test in co-simulation.
The paper uses Synopsys VCS as an RTL simulator to capture coverage scores from test sequences.
DejaVuzz uses Synopsys VCS as the industry-standard RTL simulator for simulation.
The RACE solver is a constraint solver available within Synopsys VCS.
RISCV-DV has been verified with Synopsys VCS simulator
Synopsys VCS supports simulation of RTL designs and various HDLs.
ZP Cosim supports simulation using Synopsys VCS as a backend
Synopsys VCS simulates hardware designs from RTL code to generate coverage metrics.
Synopsys VCS generates FSM coverage as one of the hardware coverage metrics.
The constraint solver used is part of Synopsys VCS.
The testcase extraction feature was provided in the VCS 2009.12 release.
Synopsys VCS implements a constraint solver used in the hierarchical test generation.
Synopsys VCS implements a BDD solver mode for constraint resolution.
CITATIONS
5 sources5 citations — click to expand
[1] Synopsys VCS is described as an industry-standard commercial tool used to simulate hardware RTL designs, translating hardware modules to Verilog and compiling them into a host executable through the VCS RTL simulator. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
[2] RISCV-DV is a SystemVerilog/UVM-based open-source RISC-V instruction generator, requires an RTL simulator supporting SystemVerilog and UVM 1.2, and has been verified with Synopsys VCS among other simulators. chipsalliance/riscv-dv
[3] The VCS constraint profiler analyzes generator performance for runtime and memory and reports runtime information by cumulative randomize calls, per randomize call, and per partition. Generating AMD microcode stimuli using VCS constraint solver
[4] VCS can partition a randomize call into several partitions when unrelated random variables occur within the same randomize call, allowing unrelated variables to be solved independently. Generating AMD microcode stimuli using VCS constraint solver
[5] The AMD microcode stimulus-generation article describes reducing randomization problem size by splitting opcode randomization into multiple smaller opcode-category classes with shared base-class constraints and category-specific child-class constraints. Generating AMD microcode stimuli using VCS constraint solver