Synopsys VCS

Tool

Synopsys VCS is documented in the provided evidence as an industry-standard commercial RTL simulator used to compile Verilog RTL into host executables for simulation, and as a verified simulator option for the RISCV-DV SystemVerilog/UVM instruction generator. Evidence also describes VCS constraint-solving/profiling behavior for constrained-random generator performance analysis.

First seen 5/24/2026

Last seen 6/6/2026

Evidence 9 chunks

Wiki v2

WIKI

Synopsys VCS

Synopsys VCS is an RTL simulation tool used in hardware verification workflows. In the MorFuzz processor-fuzzing evaluation, the authors describe using Synopsys VCS as an "industry-standard commercial tool" to simulate hardware RTL designs. Their flow translates hardware modules to Verilog and compiles them into a host executable binary through the Synopsys VCS RTL simulator.

Use in RISC-V verification flows

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NEIGHBORHOOD

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RELATIONSHIPS

17 connections

VCS Constraint Profiler ← part of 95% 4e

The VCS Constraint Profiler is a feature within Synopsys VCS.

AMD ← uses 90% 3e

AMD uses Synopsys VCS as the constraint solver in their verification flow.

MorFuzz ← uses 100% 2e

MorFuzz compiles hardware modules into a host executable binary through Synopsys VCS RTL simulator.

Hierarchical Constrained-Random Test Generation ← uses 95% 2e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver for generation.

riscv-dv ← evaluates 1e

RISCV-DV has been verified with Synopsys VCS.

Constraint Solver ← part of 90% 1e

The constraint solver used is part of Synopsys VCS.

Testcase Extraction Feature ← part of 90% 1e

The testcase extraction feature was provided in the VCS 2009.12 release.

Constraint Solver implements → 1e

Synopsys VCS implements a constraint solver used in the hierarchical test generation.

BDD Solver implements → 1e

Synopsys VCS implements a BDD solver mode for constraint resolution.

RACE Solver implements → 1e

Synopsys VCS implements the RACE solver as its default constraint solving mode.

hierarchical constrained-random stimulus generation ← uses 95% 1e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver.

ProcessorFuzz ← uses 90% 1e

ProcessorFuzz uses Synopsys VCS to report industry-standard RTL coverage metrics.

Synopsys published by → 95% 1e

Synopsys VCS is a product developed and published by Synopsys.

RTL Simulation implements → 100% 1e

Synopsys VCS is an RTL simulator.

RACE Solver ← part of 90% 1e

The RACE solver is a constraint solver available within Synopsys VCS.

BDD Solver ← part of 90% 1e

The BDD solver is a constraint solver available within Synopsys VCS.

Testcase Extraction Feature introduces → 95% 1e

VCS 2009.12 introduced a testcase extraction feature to extract the slowest partition from each randomize call.

LINKED ENTITIES

4 links

Hierarchical Constrained-Random Test Generation USES Extracted graph relationship

VCS Constraint Profiler PART_OF Extracted graph relationship

Constraint Solver PART_OF Extracted graph relationship

Testcase Extraction Feature PART_OF Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Synopsys VCS is described as an industry-standard commercial tool used to simulate hardware RTL designs, translating hardware modules to Verilog and compiling them into a host executable through the VCS RTL simulator. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[2] RISCV-DV is a SystemVerilog/UVM-based open-source RISC-V instruction generator, requires an RTL simulator supporting SystemVerilog and UVM 1.2, and has been verified with Synopsys VCS among other simulators. chipsalliance/riscv-dv

[3] The VCS constraint profiler analyzes generator performance for runtime and memory and reports runtime information by cumulative randomize calls, per randomize call, and per partition. Generating AMD microcode stimuli using VCS constraint solver

[4] VCS can partition a randomize call into several partitions when unrelated random variables occur within the same randomize call, allowing unrelated variables to be solved independently. Generating AMD microcode stimuli using VCS constraint solver

[5] The AMD microcode stimulus-generation article describes reducing randomization problem size by splitting opcode randomization into multiple smaller opcode-category classes with shared base-class constraints and category-specific child-class constraints. Generating AMD microcode stimuli using VCS constraint solver