hierarchical constrained-random stimulus generation

Technique

First seen 5/29/2026

Last seen 6/5/2026

Evidence 3 chunks

NEIGHBORHOOD

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The hierarchical approach partitions opcode constraints into a class hierarchy.

The generator uses knobs and weights to control opcode distribution.

The upper layer of the generator uses a SystemVerilog random sequence construct.

Synopsys VCS uses → 95% 1e

The hierarchical constrained-random approach uses the Synopsys VCS constraint solver.

The hierarchical approach is presented as an improvement over sequential instruction field randomization.

The hierarchical approach can use the BDD solver for constraint solving.

The hierarchical approach can also use the RACE solver for constraint solving.

The hierarchical approach targets CPU opcode generation as its primary use case.

op_gen.sv ← implements 90% 1e

op_gen.sv is the SystemVerilog file implementing the opcode generator using hierarchical constrained-random stimulus generation.

AMD ← uses 88% 1e

AMD researchers developed and use the hierarchical constrained-random stimulus generation approach.

The hierarchical constrained-random approach implements constrained-random verification principles.

The hierarchical approach provides optimal distribution and biasing for opcode generation.

The hierarchical approach leverages SystemVerilog constraint language constructs.